Co-fired passive integrated circuit devices

Patent metadata

Field	Value
Publication number	US-10062838-B2
Application number	US-201514827147-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Mar 31, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A variety of integrated circuit devices and a method for their formation and integration are provided. The integrated circuit devices may include inductors, capacitors, and/or other passive devices. In an exemplary embodiment, a first substrate is received and a conductive material is applied to the first substrate such that a loop of the conductive material is formed on the first substrate. A magnetic material is applied to the first substrate and surrounds at least a portion of the loop. A thermal process is performed on the first substrate having the conductive material and the magnetic material applied thereupon. The conductive material is bonded to a second substrate, and thereafter, the conductive material and the magnetic material are separated from the first substrate.

First claim

What is claimed is:

1. A method comprising:
receiving a carrier substrate;
forming at least one passive device structure on the carrier substrate;
firing the carrier substrate after the forming of the at least one passive device structure;
bonding the carrier substrate to a circuit substrate via a bonding structure that facilitates electrical coupling and a dummy bonding structure that facilitates physical coupling without electrical coupling, wherein the bonding includes electrically coupling the at least one passive device structure to a circuit element of the circuit substrate; and
separating the carrier substrate from the at least one passive device structure after the bonding.

2. The method of claim 1 further comprising dicing the carrier substrate to form a plurality of dies prior to the bonding, wherein the bonding couples a die of the plurality of dies to the circuit substrate.

3. The method of claim 1 , wherein the at least one passive device structure includes a capacitor, and wherein the forming of the at least one passive device structure includes:
depositing a first conductor on the carrier substrate to form a bottom plate of the capacitor;
depositing a dielectric material on the bottom plate of the capacitor; and
depositing a second conductor on the dielectric material to form a top plate of the capacitor.

4. The method of claim 3 , wherein the dielectric material has at least one opening exposing the first conductor of the bottom plate, and wherein the forming of the at least one passive device structure further includes depositing a third conductor within the at least one opening of the dielectric material to form a contact electrically coupled to the bottom plate.

5. The method of claim 1 , wherein the at least one passive device structure includes an inductor, and wherein the forming of the at least one passive device structure includes:
depositing a first magnetic material on the carrier substrate;
depositing a conductor on the first magnetic material; and
depositing a second magnetic material on the first magnetic material and the conductor such that the first magnetic material and the second magnetic material encapsulate at least a portion of the conductor.

6. The method of claim 5 , wherein the forming of the at least one passive device structure further includes depositing a dielectric material directly on the conductor, and wherein the first magnetic material and the second magnetic material further encapsulate the dielectric material.

7. The method of claim 1 , wherein the bonding the carrier substrate to the circuit substrate includes forming a first eutectic bond between bonding materials disposed on the circuit substrate and the at least one passive device structure to form the bonding structure and forming a second eutectic bond between bonding materials disposed on the circuit substrate and the at least one passive device structure to form the dummy bonding structure.

8. The method of claim 1 , wherein the bonding structure and the dummy bonding structure include gold (Au).

9. The method of claim 1 , wherein the bonding the carrier substrate to the circuit substrate includes forming a first solder bond between bonding materials disposed on the circuit substrate and the at least one passive device structure to form the bonding structure and forming a second solder bond between bonding materials disposed on the circuit substrate and the at least one passive device structure to form the dummy bonding structure.

10. The method of claim 1 , wherein the circuit element of the circuit substrate is a voltage converter.

11. The method of claim 1 , wherein the circuit element of the circuit substrate is an I/O transceiver.

12. A method comprising:
forming an inductor and a capacitor over a carrier substrate;
thereafter, firing the carrier substrate;
thereafter, bonding the carrier substrate to a circuit substrate via a bonding structure that facilitates electrical coupling and a dummy bonding structure that facilitates physical coupling without electrical coupling, such that the inductor and the capacitor are electrically coupled to the circuit substrate; and
thereafter, separating the carrier substrate from the inductor and the capacitor.

13. The method of claim 12 , wherein the forming the inductor and the capacitor includes:
forming a patterned first conductive material to define an inductor contact and a capacitor contact over the carrier substrate;
forming a patterned first magnetic material to define a first portion of the inductor disposed over the inductor contact;
forming a patterned second conductive material to define a first plate of the capacitor disposed over the capacitor contact and a loop of the inductor disposed over the first portion of the inductor;
forming a patterned dielectric material to define a dielectric of the capacitor disposed over the first plate of the capacitor;
forming a patterned second magnetic material to define a second portion of the inductor disposed over the loop of the inductor; and
forming a patterned third conductive material to define a second plate of the capacitor disposed over the dielectric of the capacitor.

14. The method of claim 13 , wherein the patterned third conductive material further defines a first conductive feature disposed on the loop of the inductor and a second conductive feature disposed on the second portion of the inductor, wherein the first conductive feature is coupled to the bonding structure and the second conductive feature is coupled to the dummy bonding structure.

15. The method of claim 12 , wherein the inductor and the capacitor are electrically coupled to a voltage converter of the circuit substrate.

16. A method comprising:
forming a passive device over a carrier substrate;
thereafter, firing the carrier substrate;
thereafter, forming a bonding structure between the passive device and a circuit substrate that electrically couples the passive device to the circuit substrate and a dummy bonding structure between the passive device and the circuit substrate that physically couples the passive device to the circuit substrate; and
thereafter, separating the carrier substrate from the passive device.

17. The method of claim 16 , wherein the bonding structure and the dummy bonding structure are formed by eutectic bonds.

18. The method of claim 16 , wherein the bonding structure and the dummy bonding structure are formed by solder bonds.

19. The method of claim 16 , wherein the bonding structure and the dummy bonding structure are disposed on a first side of the passive device and the carrier substrate is separated from a second side of the passive device that is opposite the first side.

20. The method of claim 16 , wherein the passive device is an inductor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Apple

Inventors

• Kalnitsky Alexander
• Searles Shawn
• Cappabianca David

Classifications

• H05K2203/1131

  Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity · CPC title

• H05K2201/086

  for inductive purposes, e.g. printed inductor with ferrite core · CPC title

• H05K3/4664

  Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence) · CPC title

• H05K3/007

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title