Thin film transistor and operating method thereof

Patent metadata

Field	Value
Publication number	US-10062789-B2
Application number	US-201615346798-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Nov 11, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A thin film includes a substrate, a bottom gate, a channel layer, a source and a drain, and a top gate. The bottom gate is disposed on the substrate. The channel layer is disposed on the bottom gate. The source and the drain are disposed on two different sides of the channel layer. The top gate is disposed on the channel layer, wherein the channel layer is disposed between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other. A related method is also provided.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a substrate;
a bottom gate, disposed above the substrate;
a channel layer, disposed above the bottom gate;
a source and a drain, electrically coupled to the channel layer; and
a top gate, located above the channel layer, wherein the bottom gate is configured to receive a first voltage potential, the top gate is configured to receive a second voltage potential, and the second voltage potential is less than the first voltage potential, to turn off the thin film transistor,
wherein the top gate is configured to receive a ground voltage, while the bottom gate is configured to receive a voltage greater than the ground voltage, to turn on the thin film transistor.

2. A thin film transistor, comprising:
a substrate;
a bottom gate, disposed above the substrate;
a channel layer, located above the bottom gate;
a source and a drain, electrically coupled to the channel layer; and
a top gate, located above the channel layer, wherein the channel layer is located between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other,
wherein the bottom gate is configured to receive a ground voltage, while the top gate is configured to receive a voltage less than the ground voltage, to turn off the thin film transistor.

3. The thin film transistor of claim 2 , wherein the bottom gate and the top gate are connected to different scan lines respectively.

4. The thin film transistor of claim 2 , wherein the top gate is configured to receive the ground voltage, while the bottom gate is configured to receive a voltage greater than the ground voltage, to turn on the thin film transistor.

5. A thin film transistor, comprising:
a substrate;
a bottom gate, disposed above the substrate;
a channel layer, located above the bottom gate;
a source and a drain, electrically coupled to the channel layer; and
a top gate, located above the channel layer, wherein the channel layer is located between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other, wherein the top gate is configured to receive a ground voltage, while the bottom gate is configured to receive a voltage greater than the ground voltage, to turn on the thin film transistor.

6. The thin film transistor of claim 5 , wherein a width of a region of the top gate overlapping with the channel layer in a projection direction is greater than 1 μm.

7. The thin film transistor of claim 2 , wherein a width of a region of the top gate overlapping with the channel layer in a projection direction is at least greater than 1 μm.

8. An operating method of a thin film transistor having a substrate, a bottom gate disposed above the substrate, a channel layer located above the bottom gate, a source and a drain electrically coupled to the channel layer, a top gate, located above the channel layer, wherein the channel layer is located between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other, the operating method comprising:
receiving a ground voltage by the bottom gate;
simultaneously receiving a voltage less than the ground voltage by the top gate; and
turning off the thin film transistor in response to the simultaneously-received voltages.

9. The operating method of claim 8 , wherein a voltage difference between the bottom gate and the top gate is at least equal to or greater than a threshold voltage of the transistor to turn off the thin film transistor.

10. The operating method of claim 8 , wherein a voltage difference between the bottom gate and the top gate is at least equal to or greater than a threshold voltage of the transistor to turn on the thin film transistor.

11. The operating method of claim 8 , further comprising receiving the ground voltage by the top gate, while receiving a voltage greater than the ground voltage by the bottom gate, to turn on the thin film transistor.

12. The operating method of claim 11 , wherein a voltage difference between the bottom gate and the top gate is at least equal to or greater than a threshold voltage of the transistor to turn off the thin film transistor.

13. The operating method of claim 11 , wherein a voltage difference between the bottom gate and the top gate is at least equal to or greater than a threshold voltage of the transistor to turn on the thin film transistor.

14. The thin film transistor of claim 5 , wherein the bottom gate and the top gate are connected to different scan lines respectively.

Assignees

• Au Optronics Corp

Inventors

• Yang yu-xin
• Chen Kuo-Kuang
• Shih Tsung-Hsiang
• Tsai Ming-Yen
• Chang Ting-Chang

Classifications

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/78648 Primary

  Electricity · mapped topic

• H03K2017/6878

  using multi-gate field-effect transistors · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title