Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10062761-B2
Application number	US-201514730851-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	May 31, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A method for manufacturing a semiconductor device includes steps of forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction; forming a conductive layer in the trench, with a first insulating film interposed therebetween; dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film; introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along an opening portion of the trench so as to come into contact with the opening portion.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device comprising:
forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction;
forming a conductive layer in the trench, with a first insulating film interposed therebetween, so as to be buried in the entire trench;
forming a third insulating film on the conductive layer;
forming an opening in the third insulating film;
etching the conductive layer, via the opening in the third insulating film, thereby dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film, thereby covering at least a portion of the third insulating film that is not subsequently removed;
introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and
selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along the trench so as to come into contact with the trench.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the channel forming region is formed before the conductive layer is divided.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein forming the channel forming region includes implanting second-conductivity-type impurity ions into the entire surface of the semiconductor substrate.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein forming the main electrode region includes selectively implanting first-conductivity-type impurity ions into the channel forming region.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the conductive layer is a polysilicon layer doped with impurities.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is formed by thermally oxidizing the semiconductor substrate, and the second insulating film is any one of an HTO film, an organic silicon compound film, a PSG film, and a BPSG film.

7. The method for manufacturing a semiconductor device according to claim 2 , wherein forming the channel forming region includes implanting second-conductivity-type impurity ions into the entire surface of the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 2 , wherein forming the main electrode region includes selectively implanting first-conductivity-type impurity ions into the channel forming region.

9. The method for manufacturing a semiconductor device according to claim 2 , wherein the conductive layer is a polysilicon layer doped with impurities.

10. The method for manufacturing a semiconductor device according to claim 2 , wherein the first insulating film is formed by thermally oxidizing the semiconductor substrate, and the second insulating film is any one of an HTO film, an organic silicon compound film, a PSG film, and a BPSG film.

11. The method for manufacturing a semiconductor device according to claim 1 , wherein the opening is formed in a portion of the third insulating film corresponding to a center of the trench.

12. The method for manufacturing a semiconductor device according to claim 2 , wherein the opening is formed in a portion of the third insulating film corresponding to a center of the trench.

13. The method for manufacturing a semiconductor device according to claim 1 , wherein when filling the gap between the gate electrode and the in-trench wiring layer with the second insulating film, the second insulating film is formed directly on the third insulating film.

14. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming an electrode on the second insulating film.

15. The method for manufacturing a semiconductor device according to claim 1 , further comprising:
forming an opening portion in the second insulating film and the third insulating film; and
forming an electrode in the opening portion such that the electrode is formed directly on at least a sidewall of the second insulating film, a sidewall of the third insulating film, and the channel forming region.

16. The method for manufacturing a semiconductor device according to claim 1 , wherein when introducing the second-conductivity-type impurities into the entire surface of the semiconductor substrate to form the channel forming region of the second conductivity type, the second-conductivity-type impurities are introduced without using a mask.

Assignees

• Fuji Electric Co Ltd

Inventors

• Yoshimoto Atsushi

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title