Semiconductor device, and semiconductor chip having chip identification information

US10062650B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10062650-B2
Application numberUS-201415324094-A
CountryUS
Kind codeB2
Filing dateSep 1, 2014
Priority dateSep 1, 2014
Publication dateAug 28, 2018
Grant dateAug 28, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device employs at least one of semiconductor chip groups. The semiconductor device includes a semiconductor chip included in the semiconductor chip groups, and a package. The semiconductor chip includes an information recording region on which is recorded a first piece of identification information indicating to which group of the semiconductor chip groups the semiconductor chip belongs based on a first category. The information recording region includes a plurality of fuses selectively blown in accordance with the first piece of identification information. Indicated on the package is a second piece of identification information indicating to which group of the semiconductor chip groups the semiconductor chip belongs based on a second category. The first and second pieces of identification information are combined together to identify the semiconductor chip from among the semiconductor chip groups.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device employing at least one of semiconductor chip groups, comprising: one semiconductor chip included in said semiconductor chip groups, said one semiconductor chip including an information recording region on which is recorded a first piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a first category, said information recording region including a plurality of fuses selectively blown in accordance with said first piece of identification information; and a package sealing said semiconductor chip therein, said package having a second piece of identification information indicated thereon, said second piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a second category, said first and second pieces of identification information being combined together to identify said one semiconductor chip from among said semiconductor chip groups, wherein said first piece of identification information alone does not uniquely identify said one semiconductor chip. 2. The semiconductor device according to claim 1 , further comprising at least one information output electrode electrically connected to said information recording region of said semiconductor chip and extending to the outside of said package. 3. A semiconductor device employing at least one of semiconductor chip groups, comprising: one semiconductor chip included in said semiconductor chip groups, said one semiconductor chip including an information recording region on which is recorded a first piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a first category, said information recording region including a plurality of fuses selectively blown in accordance with said first piece of identification information; and a package sealing said semiconductor chip therein, said package having a second piece of identification information indicated thereon, said second piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a second category, said first and second pieces of identification information being combined together to identify said one semiconductor chip from among said semiconductor chip groups, wherein said information recording region included in said semiconductor chip includes a circuit pattern in accordance with said first piece of identification information, and said fuses and said circuit pattern record said first piece of identification information thereon in a shared manner. 4. A semiconductor chip being one semiconductor chip of semiconductor chip groups, comprising: a first partial recording region on which is recorded a first piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a first category, said first partial recording region including a plurality of fuses selectively blown in accordance with said first piece of identification information; and a second partial recording region on which is recorded a second piece of identification information indicating to which group of said semiconductor chip groups said one semiconductor chip belongs based on a second category, said second partial recording region including a circuit pattern patterned in accordance with said second piece of identification information, said first and second pieces of identification information being combined together to identify said one semiconductor chip from among said semiconductor chip groups. 5. The semiconductor chip according to claim 4 , further comprising at least one output terminal electrically connected to an information recording region having said first and second partial recording regions. 6. The semiconductor chip according to claim 5 , further comprising an analog signal output circuit for outputting an analog signal corresponding to said information recording region from said output terminal. 7. The semiconductor chip according to claim 6 , wherein said analog signal includes at least one selected from the group consisting of a voltage signal, a current signal and a pulse signal. 8. The semiconductor chip according to claim 6 , wherein said analog signal output circuit outputs a reference signal serving as a comparison criterion for said analog signal. 9. The semiconductor chip according to claim 6 , wherein said analog signal output circuit receives a reference signal serving as a comparison criterion for said analog signal. 10. The semiconductor chip according to claim 5 , further comprising a digital signal output circuit for outputting a digital signal corresponding to said information recording region from said output terminal. 11. The semiconductor chip according to claim 5 , wherein said output terminal is provided for each of pieces of identification information.

Assignees

Inventors

Classifications

  • comprising an arrangement for testing the record carrier · CPC title

  • Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

  • for non-wireless electrical read out · CPC title

  • for identification or tracking · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10062650B2 cover?
A semiconductor device employs at least one of semiconductor chip groups. The semiconductor device includes a semiconductor chip included in the semiconductor chip groups, and a package. The semiconductor chip includes an information recording region on which is recorded a first piece of identification information indicating to which group of the semiconductor chip groups the semiconductor chip…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10W46/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).