Semiconductor devices comprising nickel- and copper-containing interconnects

Patent metadata

Field	Value
Publication number	US-10062608-B2
Application number	US-201715584226-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	Sep 2, 2004
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a conductive interconnect extending through a thickness of a substrate, the conductive interconnect comprising a first layer including nickel surrounding an inner core including copper; and
a bond pad on the substrate, the bond pad surrounding an end of the conductive interconnect, the bond pad being electrically coupled to the conductive interconnect by a second layer including nickel.

2. The semiconductor device of claim 1 , wherein the first layer is between about 0.05 μm and about 10 μm.

3. The semiconductor device of claim 1 , wherein the first layer is between about 3 μm and about 5 μm.

4. The semiconductor device of claim 1 , wherein the conductive interconnect further comprises a layer including tungsten surrounding the first layer and the inner core.

5. The semiconductor device of claim 4 , wherein the layer including tungsten is between about 0.02 μm and about 1 μm.

6. The semiconductor device of claim 4 , wherein the conductive interconnect further comprises a layer including titanium nitride surrounding the layer including tungsten.

7. The semiconductor device of claim 6 , wherein the layer including tungsten is between about 50 Å and about 200 Å.

8. The semiconductor device of claim 1 , wherein the inner core of the conductive interconnect comprises copper and one or more of silver, tin, lead, indium and antimony.

9. The semiconductor device of claim 1 , wherein the bond pad comprises copper, aluminum, or combinations thereof.

10. The semiconductor device of claim 1 , wherein the bond pad is separated from the conductive interconnect by an oxide layer surrounding the conductive interconnect.

11. The semiconductor device of claim 10 , wherein the oxide layer is between about 0.1 μm and about 5 μm.

12. The semiconductor device of claim 10 , wherein the oxide layer is between about 1 μm and about 2 μm.

13. The semiconductor device of claim 10 , wherein the oxide layer is a low stress oxide (“LSO”) layer.

14. The semiconductor device of claim 1 , wherein the second layer is between about 0.05 μm and about 10 μm.

15. The semiconductor device of claim 1 , wherein the second layer is disposed over the bond pad.

16. The semiconductor device of claim 1 , wherein a ratio of the thickness of the substrate and a diameter of the conductive interconnect is between about 4:1 and 30:1.

17. A semiconductor device, comprising:
a conductive interconnect extending through a thickness of a substrate, the conductive interconnect comprising a first layer including nickel surrounding an inner core including copper, and a second layer including tungsten surrounding the first layer and the inner core; and
a copper bond pad on the substrate, the copper bond pad surrounding an end of the conductive interconnect, the copper bond pad being electrically coupled to the conductive interconnect by a third layer including nickel disposed over the copper bond pad.

18. The semiconductor device of claim 17 , further comprising an integrated circuit on a first side of the substrate, wherein the conductive interconnect electrically couples the integrated circuit to a component or apparatus on a second side of the substrate.

19. The semiconductor device of claim 18 , wherein the semiconductor device is arranged in a stack of semiconductor devices and wherein the conductive interconnect electrically couples the integrated circuit to another one of the stack of semiconductor devices.

20. A semiconductor device, comprising:
an interconnect extending through a substrate, the interconnect comprising a nickel material surrounding a material comprising copper; and
a bond pad surrounding an end of the interconnect, the bond pad electrically coupled to the interconnect by another nickel material.

Assignees

• Micron Technology Inc

Inventors

• Akram Salman
• Wark James M
• Hiatt William Mark

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title