Self-test GFCI device with dual solenoid coil electric control

US10062535B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10062535-B2
Application numberUS-201414156036-A
CountryUS
Kind codeB2
Filing dateJan 15, 2014
Priority dateJan 15, 2014
Publication dateAug 28, 2018
Grant dateAug 28, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit interrupting device having a dual-coil solenoid for delivering an increased magnetic field to the solenoid plunger when a fault is detected and it is desired to place the device into a tripped condition. Independent switching devices control the flow of current through the respective coils of the solenoid and a third switching device controls the operation of the two coil driving switch devices. A detection circuit detects faults and controls the third switching device to activate the coil driving switching devices when a fault is detected. A programmable device runs a self-test program to determine whether the device is operating properly and faults can be detected. The programmable device can also independently control the operation of the two coil driving switching devices.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit interrupting device comprising: one or more line conductors for electrically connecting to an external power supply; one or more load conductors for electrically connecting to an external load; and a current interrupter that disconnects said line conductors from said load conductors when said circuit interrupting device is in a tripped condition and allows said line conductors and said load conductors to be electrically connected when said circuit interrupting device is in a reset condition, said current interrupter including, a solenoid with at least a first winding that generates a respective first magnetic force on an armature when said first winding is electrically energized and a second winding that generates a respective second magnetic force on said armature when said second winding is electrically energized, wherein a third magnetic force which is larger in magnitude than the sum of said first and second magnetic forces is generated on said armature when both said first and second windings are electrically energized at the same time. 2. The circuit interrupting device recited in claim 1 , further comprising: a first switching device that electrically energizes said first winding when said first switching device is activated; and a second switching device that electrically energizes said second winding when said second switching device is activated. 3. The circuit interrupting device recited in claim 2 , further comprising: a sense transformer through which said line and load conductors pass, said sense transformer generating a secondary current signal that is indicative of a difference between a current flowing on said line conductors and a current flowing on said load conductors; a GFCI device that receives said secondary current signal and generates a switch control signal if said secondary current signal exceeds a predetermined threshold value; and a third switching device that receives said switch control signal from said GFCI device and electrically activates said first and second switching devices when said secondary current signal exceeds said predetermined threshold value. 4. The circuit interrupting device recited in claim 3 , wherein said third switching device blocks one or more feedback signals generated by one or more of said first and second switching devices. 5. The circuit interrupting device recited in claim 1 , further comprising: a fault detection circuit that detects a fault condition in said circuit interrupting device and generates a fault detection signal when said fault condition is detected, wherein said fault detection signal is provided to said current interrupter to place said circuit interrupting device in said tripped condition; and an auto-monitoring circuit electrically coupled to said fault detection circuit and said current interrupter and continuously monitoring one or more signals to determine an operating state of said circuit interrupting device. 6. The circuit interrupting device recited in claim 5 , wherein at least one selected from the group consisting of said monitored signals includes a first auto-monitoring input signal the value of which is at least partially determined by a value of a pre-trigger signal generated by said fault detection circuit, wherein said pre-trigger signal does not activate said interrupting device to place said circuit interrupting device in said tripped condition. 7. The circuit interrupting device recited in claim 6 , wherein said fault detection circuit includes a GFCI device that detects a net current flowing from said line conductors to said load conductors and generates said pre-trigger signal when said net current exceeds a predetermined threshold. 8. The circuit interrupting device recited in claim 7 , wherein said GFCI device generates a trigger signal to activate said current interrupter to place said circuit interrupting device in said tripped condition when said net current exceeds the predetermined threshold for a predetermined amount of time. 9. A wiring device comprising: a terminal configured to receive power; a dual-coil solenoid having first and second windings, said first winding having first and second pins, said first pin configured to receive power from the terminal, said second winding having third and fourth pins, said third pin configured to receive power from the terminal; a fault detection circuit configured to detect one or more fault conditions in said wiring device and generate trigger signal when said fault condition meets predetermined criteria, wherein said one or more fault conditions includes a self-test fault condition; a programmable circuit device programmed to execute an auto-monitoring routine that generates a self-test fault signal, wherein said self-test fault signal generates said self-test fault condition in said wiring device; a first switching device activated to conduct current by said trigger signal received from said fault detection circuit; a second switching device electrically connected to said first switching device and said second pin, said second switching device activated when said first switching device conducts current; and a third switching device electrically connected to said first switching device and said fourth pin, said third switching device electrically connected between said fourth pin and a grounding element, said third switching device activated when said first switching device conducts current, wherein said first switching device electrically isolates said second and third switching devices from said fault detection circuit; wherein said first winding generates a first magnetic field when current flows through said first winding and said second winding generates a second magnetic field when current flows through said second winding; and wherein a third magnetic field is generated when current flows through said first and second windings simultaneously and said third magnetic field is greater than the sum of said first and second magnetic fields. 10. The wiring device recited in claim 9 , wherein at least one selected from the group consisting of said first, second, and third switching devices is a silicon controlled rectifier device. 11. The wiring device recited in claim 10 , wherein said fault detection circuit includes a 4141 GFCI chip. 12. The wiring device recited in claim 9 , wherein said fault detection circuit includes a commercially available GFCI chip that includes at least two input/output (I/O) ports, wherein one of said I/O ports outputs said trigger signal and another of said I/O ports outputs a pre-trigger signal and said pre-trigger signal is generated before said trigger signal is generated. 13. The wiring device recited in claim 12 , wherein said pre-trigger signal is delivered to said fault detection circuit on a pre-trigger conductor. 14. The wiring device recited in claim 13 , further comprising a filter capacitor electrically connected between said pre-trigger conductor and electrical ground, wherein the value of said filter capacitor is selected to eliminate noise from causing false trigger signals, when a fault is not detected, and still be able to charge fast enough such that the wiring device is placed in the trip condition within the time required by standard UL-943 when a fault is detected. 15. A circuit interrupting device comprising: one or more line conductors for electrically connecting to an external power supply; one or more load conductors for electrically connecting to an external load; an interrupting device connected to said line conductors and said load conductors and electrically co

Assignees

Inventors

Classifications

  • the main function being self testing of the device · CPC title

  • with means for increasing reliability, e.g. redundancy arrangements {(for logic circuits H03K19/003)} · CPC title

  • Monitoring, detection or measuring systems to establish the end of life of the switching device, can also contain other on-line monitoring systems, e.g. for detecting mechanical failures · CPC title

  • H01H83/04Primary

    with testing means for indicating the ability of the switch or relay to function properly · CPC title

  • characterised by the coil design · CPC title

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What does patent US10062535B2 cover?
A circuit interrupting device having a dual-coil solenoid for delivering an increased magnetic field to the solenoid plunger when a fault is detected and it is desired to place the device into a tripped condition. Independent switching devices control the flow of current through the respective coils of the solenoid and a third switching device controls the operation of the two coil driving swit…
Who is the assignee on this patent?
Hubbell Inc
What technology area does this patent fall under?
Primary CPC classification H01H83/04. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).