Rendering apparatus and method

Patent metadata

Field	Value
Publication number	US-10062138-B2
Application number	US-201615158002-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Sep 11, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Provided are apparatuses and methods for rendering. The methods analyze draw commands and graphics states, generate hierarchical graphics states from the graphics states based on a graphics state common to the draw commands, and perform rendering of an image frame based on the hierarchical graphics states. The apparatuses use a hierarchical state generator and a graphics processing unit (GPU) to perform the rendering method.

First claim

What is claimed is:

1. A rendering apparatus, comprising:
a hierarchical state generator configured to analyze draw commands of at least one image frame and graphics states for rendering the at least one image frame, and to generate therefrom hierarchical graphics states comprising a first hierarchical graphics state comprised of at least one graphics state common to the draw commands, and second hierarchical graphics states which are draw states each corresponding to a respective one of the draw commands, each differing from the first hierarchical graphics states; and
a graphics processing unit (GPU) configured to render the at least one image frame based on the hierarchical graphics states;
wherein the GPU is further configured to render the at least one image frame using a plurality of graphics pipeline stages of a graphics pipeline, the first hierarchical graphics state is an image state comprised of at least one graphics state associated with at least one of the graphics pipeline stages, and each of the draw states is comprised of graphics states that are each associated with remaining ones of the graphics pipeline stages.

2. The rendering apparatus of claim 1 , wherein the GPU comprises:
a state manager configured to set the image state and the draw states to be used by the graphics pipeline, wherein
the graphics pipeline is configured to render the at least one image frame based on the image state and the draw states set by the state manager.

3. The rendering apparatus of claim 2 , wherein the state manager sets the draw states to be used sequentially by the graphics pipeline after setting the image state to be used by the graphics pipeline.

4. The rendering apparatus of claim 1 , wherein the CPU comprises:
a tile binner configured to divide the at least one image frame into tiles and to generate binning information representing which tiles among the tiles correspond to each of the draw states;
a state manager configured to determine a graphics state contained commonly in draw states corresponding to a predetermined tile as a tile state based on the binning information; and
the graphics pipeline is configured to render the predetermined tile based on the hierarchical graphics states and the tile state.

5. The rendering apparatus of claim 4 , wherein the state manager is configured to determine, based on the tile state, tile draw states containing graphics states other than those of the tile state, the tile draw states being respective ones of the draw states corresponding to the predetermined tile, and to set the image state, the tile state, and the tile draw states to be used by the graphics pipeline.

6. The rendering apparatus of claim 5 , wherein the state manager is configured to set the tile draw states to be used sequentially by the graphics pipeline after sequentially setting the image state and the tile state to be used by the graphics pipeline.

7. The rendering apparatus of claim 1 , wherein the hierarchical state generator is configured to generate the hierarchical graphics states for every rendering pass for a multi-pass rendering of the at least one image frame, and
wherein the GPU is configured to perform the multi-pass rendering of the at least one image frame based on the hierarchical graphics states generated for each rendering pass.

8. The rendering apparatus of claim 1 , wherein the hierarchical state generator is configured to provide the GPU with the hierarchical graphics states by using a state vector.

9. The rendering apparatus of claim 1 , wherein the graphics pipeline stages comprise an input assembly (IA), a vertex shader (VS), a primitive assembly (PA), a rasterizer (RAS) and a primitive shader (PS), and the first hierarchical graphics state is comprised of a plurality of graphics states respectively used for at least two of the IA, the VS, the PA, the RAS and the PS.

10. The rendering apparatus of claim 1 , wherein, for the rendering of the at least one image frame, the hierarchical state generator transmits to the GPU the first hierarchical graphics state and information of changed graphics states between the draw states, and refrains from transmitting remaining ones of the graphics states used for the rendering.

11. A rendering method, comprising:
analyzing draw commands and graphics states for rendering at least one image frame, and generating therefrom hierarchical graphics states comprising a first hierarchical graphics state comprised of at least one graphics state common to the draw commands, and second hierarchical graphics states which are draw states each corresponding to a respective one of the draw commands, each differing from the first hierarchical graphics state; and
rendering the at least one image frame based on the hierarchical graphics states,
wherein the rendering of the at least one image frame is performed using a plurality of graphics pipeline stages of a graphics pipeline, the first hierarchical graphics state is an image state comprised of at least one graphics state associated with at least one of the graphics pipeline stages, and each of the draw states is comprised of graphics states that are each associated with remaining ones of the graphics pipeline stages.

12. The rendering method of claim 11 , wherein the rendering comprises:
setting the image state and the draw states to be used by the graphics pipeline; and
rendering the at least one image frame based on the image state and the draw states.

13. The rendering method of claim 12 , wherein the setting comprises:
setting the draw states to be used sequentially by the graphics pipeline after setting the image state to be used by the graphics pipeline.

14. The rendering method of claim 11 , wherein the rendering comprises:
dividing the at least one image frame into tiles and generating binning information representing which tiles among the tiles correspond to each of the draw states;
determining a graphics state contained commonly in draw states corresponding to a predetermined tile as a tile state based on the binning information; and
rendering the predetermined tile based on the hierarchical graphics states and the tile state.

15. The rendering method of claim 14 , wherein the rendering of the predetermined tile comprises:
determining, based on the tile state, tile draw states containing graphics states other than those of the tile state, the tile draw states being respective ones of the draw states corresponding to the predetermined tile;
setting the image state, the tile state, and the tile draw states to be used by the graphics pipeline; and
rendering the predetermined tile based on the set image state, the set tile state, and the set tile draw states.

16. The rendering method of claim 15 , wherein the setting the image state, the tile state, and the tile draw states to the graphics pipeline comprises:
setting the tile draw states to be used sequentially by the graphics pipeline after sequentially setting the image state and the tile state to be used by the graphics pipeline.

17. The rendering method of claim 11 , wherein the generating the hierarchical graphics states comprises:
generating the hierarchical graphics states for every rendering pass to perform multi-pass rendering, and
wherein the rendering comprises
performing the multi-pass rendering of the at least one image frame based on the hierarchical graphics states generated for each pass.

18. The rendering method of claim 11 , wherein the graphics pipeline stages comprise an input assembly (IA), a vertex shader (VS), a primitive assembly (PA), a ras

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Minyoung
• Jeong Minkyu
• Yoo Donghoon

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2207/20016

  Hierarchical, coarse-to-fine, multiscale or multiresolution image processing; Pyramid transform · CPC title

• G09G2360/122

  Tiling · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title