Circuit design instrumentation for state visualization

Patent metadata

Field	Value
Publication number	US-10061879-B2
Application number	US-201715707293-A
Country	US
Kind code	B2
Filing date	Sep 18, 2017
Priority date	Jan 30, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.

First claim

What is claimed is:

1. A non-transitory computer-readable storage medium for interfacing with an integrated circuit, wherein at least a portion of a design-under-test is implemented in a subset of the integrated circuit, and wherein the non-transitory computer-readable storage medium comprises instructions for:
directing a local control circuit in the integrated circuit to halt a clock signal that clocks a plurality of storage circuits in the subset of the integrated circuit;
providing data from the plurality of storage circuits to a plurality of scan storage circuits using multiplexer circuits that couple the plurality of scan storage circuits together in a scan chain to enable shifting the data through the plurality of scan storage circuits after the data is loaded into the plurality of scan storage circuits from the plurality of storage circuits;
directing the local control circuit to retrieve the data stored in the plurality of storage circuits using the plurality of scan storage circuits that are arranged in the scan chain without erasing the data stored in the plurality of storage circuits;
receiving the retrieved data from the local control circuit; and
directing the local control circuit to resume the clock signal.

2. The non-transitory computer-readable storage medium defined in claim 1 , further comprising instructions for:
generating a mapping between a plurality of sequential elements in the design-under-test and the plurality of storage circuits.

3. The non-transitory computer-readable storage medium defined in claim 2 , further comprising instructions for:
sending a request to the local control circuit to retrieve data stored in a sequential element of the plurality of sequential elements; and
receiving data that is stored in a storage circuit of the plurality of storage circuits and that is retrieved in response to the request, wherein the storage circuit is selected based on the mapping.

4. The non-transitory computer-readable storage medium defined in claim 2 , further comprising instructions for:
directing the local control circuit to provide a subset of the retrieved data based on the mapping.

5. The non-transitory computer-readable storage medium defined in claim 2 , wherein the mapping is restricted to observable storage circuits in the subset of the integrated circuit.

6. The non-transitory computer-readable storage medium defined in claim 1 , wherein another subset in an additional integrated circuit with an additional plurality of storage circuits implements another portion of the design-under-test, and wherein the non-transitory computer-readable storage medium further comprises instructions for:
generating a mapping between a first plurality of sequential elements in the design-under-test and the plurality of storage circuits and between a second plurality of sequential elements in the design-under-test and the additional plurality of storage circuits.

7. A method for interfacing with an integrated circuit, wherein at least a portion of a design-under-test is implemented in a subset of the integrated circuit, and wherein the method comprises:
directing a local control circuit in the integrated circuit to halt oscillations in a clock signal that clocks a plurality of storage circuits in the subset of the integrated circuit;
providing data from the plurality of storage circuits to a plurality of scan storage circuits using multiplexer circuits that couple the plurality of scan storage circuits together in a scan chain to enable shifting the data through the plurality of scan storage circuits after the data is loaded into the plurality of scan storage circuits from the plurality of storage circuits;
directing the local control circuit to retrieve the data stored in the plurality of storage circuits using the plurality of scan storage circuits that are arranged in the scan chain without erasing the data stored in the plurality of storage circuits;
receiving the retrieved data from the local control circuit; and
directing the local control circuit to restart oscillations in the clock signal.

8. The method defined in claim 7 , further comprising:
generating a mapping between a plurality of sequential elements in the design-under-test and the plurality of storage circuits.

9. The method defined in claim 8 , further comprising:
sending a request to the local control circuit to retrieve data stored in a sequential element of the plurality of sequential elements; and
receiving data that is stored in a storage circuit of the plurality of storage circuits and that is retrieved in response to the request, wherein the storage circuit is selected based on the mapping.

10. The method defined in claim 8 , further comprising:
directing the local control circuit to provide a subset of the retrieved data based on the mapping.

11. The method defined in claim 8 , wherein the mapping is restricted to observable storage circuits in the subset of the integrated circuit.

12. The method defined in claim 7 , wherein another subset in an additional integrated circuit with an additional plurality of storage circuits implements another portion of the design-under-test, and wherein the method further comprises:
generating a mapping between a first plurality of sequential elements in the design-under-test and the plurality of storage circuits and between a second plurality of sequential elements in the design-under-test and the additional plurality of storage circuits.

13. An integrated circuit comprising:
user storage circuits, wherein at least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits;
a local control circuit; and
scan storage circuits arranged in a scan chain, wherein the local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits; and
first multiplexer circuits that provide the data from the user storage circuits to the scan storage circuits, wherein the first multiplexer circuits couple the scan storage circuits together in the scan chain to enable shifting the data through the scan storage circuits after the data is loaded into the scan storage circuits from the user storage circuits,
wherein the local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.

14. The integrated circuit of claim 13 , wherein the data is loaded into the scan storage circuits from the user storage circuits in response to a scan clock signal without shifting additional data into the user storage circuits, and wherein the scan clock signal is different from the user clock signal.

15. The integrated circuit of claim 14 ,
wherein each of the first multiplexer circuits comprises a first input coupled to an output of one of the user storage circuits and an output coupled to an input of one of the scan storage circuits, and wherein at least one of the first multiplexer circuits comprises a second input coupled to an output of one of the scan storage circuits.

16. The integrated circuit of claim 14 further comprising:
second multiplexer circuits that provide the data to the user storage circuits, wherein the second multiplexer circuits are coupled to provide additional data from the scan storage circuits to the user storage circuits during a write-back mode.

17. The integrated circuit of claim 16 , whe

Assignees

• Altera Corp

Inventors

• Hutton Michael

Classifications

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031 Primary

  Physics · mapped topic