Soft-decision input generation for data storage systems

Patent metadata

Field	Value
Publication number	US-10061640-B1
Application number	US-201313797943-A
Country	US
Kind code	B1
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

First claim

What is claimed is:

1. A data storage device comprising:
a non-volatile solid-state memory array comprising a plurality of non-volatile solid-state memory devices configured to store data; and
a controller configured to:
determine a known reference bit stream comprising a plurality of bit values recorded in a plurality of memory cells, respectively, at a reference memory location;
obtain a bit pattern for each of the plurality of memory cells at the reference memory location by performing a first plurality of reads on each of the plurality of memory cells at the reference memory location at a plurality of voltage read levels, wherein the bit pattern comprises a bit value from each of the first plurality of reads, wherein the bit pattern is correlated with a respective bit value of the reference bit stream recorded in a respective memory cell at the reference memory location;
determine probability data based at least in part on a number of occurrences of the respective bit patterns obtained for the plurality of memory cells at the reference memory location and the correlated respective bit values of the reference bit stream;
generate possible log likelihood ratios (LLRs) based at least in part on the probability data;
store the possible LLRs in association with the reference memory location;
select, in connection with a multiple read operation on a target memory location, the stored possible LLRs based on a predetermined association between the target memory location and the reference memory location;
generate a sequence of LLRs based at least in part on the selected possible LLRs and on bit patterns from a multiple read operation on a target memory location; and
decode data stored in the target memory location using the generated sequence of LLRs.

2. The data storage device of claim 1 , wherein the plurality of voltage read levels comprises at least one of a lower read level, an intermediate read level, and an upper read level.

3. The data storage device of claim 1 , wherein the target memory location comprises multiple-level cells storing an upper page and lower page, and wherein the sequence of LLRs correspond to the upper page and are based at least in part on bit values of the lower page.

4. The data storage device of claim 3 , wherein the target memory location comprises a plurality of 2-level cells.

5. The data storage device of claim 3 , wherein the target memory location comprises a plurality of 3-level cells.

6. The data storage device of claim 1 , wherein the controller is configured to use the generated sequence of LLRs when the controller is unable to decode data from the target memory location using a single read of the target memory location.

7. The data storage device of claim 1 , wherein performing the plurality of reads comprises performing three reads.

8. The data storage device of claim 1 , wherein the controller is further configured to adjust at least one of the plurality of voltage read levels based at least in part on the probability data.

9. The data storage device of claim 1 , wherein the plurality of bit values of the reference bit stream comprises an equal number of 1's and 0's.

10. The data storage device of claim 1 , wherein the controller is further configured to provide the generated sequence of LLRs to a low-density parity-check (LDPC) encoder.

11. In a data storage system comprising a non-volatile solid state memory array and a controller, a method of storing data, the method comprising:
determining a known reference bit stream comprising a plurality of bit values recorded in a plurality of memory cells, respectively, at a reference memory location;
obtaining a bit pattern for each of the plurality of memory cells at the reference memory location by performing a first plurality of reads on each the plurality of memory cells at the reference memory location at a plurality of voltage read levels wherein the bit pattern comprises a bit value from each of the first plurality of reads, wherein the bit pattern is correlated with a respective bit value of the reference bit stream recorded in a respective memory cell at the reference memory location;
determining probability data based at least in part on a number of occurrences of the respective bit patterns obtained for the plurality of memory cells at the reference memory location and the correlated respective bit values of the reference bit stream;
generating possible log likelihood ratios (LLRs) based at least in part on the probability data;
storing the possible LLRs in association with the reference memory location;
selecting, in connection with a multiple read operation on a target memory location, the stored possible LLRs based on a predetermined association between the target memory location and the reference memory location;
generating a sequence of LLRs based at least in part on the selected possible LLRs and on the bit patterns from a multiple read operation on a target memory location; and
decoding data stored in the target memory location using the generated sequence of LLRs.

12. The method of claim 11 , wherein the plurality of voltage read levels comprises at least one of a lower read level, an intermediate read level, and an upper read level.

13. The method of claim 11 , wherein the target memory location comprises multiple-level cells storing an upper page and lower page, and wherein the sequence of LLRs correspond to the upper page and are based at least in part on bit values of the lower page.

14. The method of claim 11 , wherein decoding the data from the target memory location using the generated sequence of LLRs is performed when data from the target memory location is unable to be decoded using a single read of the target memory location.

15. The method of claim 11 , further comprising adjusting at least one of the plurality of voltage read levels based at least in part on the probability data.

16. The method of claim 11 , further comprising providing the generated sequence of LLRs to a low-density parity-check (LDPC) decoder.

17. The data storage device of claim 1 , wherein the controller is further configured to:
populate at least one look-up table (LUT) with the generated sequence of LLRs;
periodically decode the data stored in the target memory location; and

update the at least one LUT based at least in part on the decoded data.

18. The method of claim 11 further comprising:
populating at least one look-up table (LUT) with the generated sequence of LLRs;
periodically decoding the data stored in the target memory location; and

updating the at least one LUT based at least in part on the decoded data.

Assignees

• Western Digital Tech Inc

Inventors

• Lu Guangming
• Anderson Kent D
• Krishnan Anantha Raman
• Dahandeh Shafa

Classifications

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title