Instruction for performing a pseudorandom number generate operation

US10061585B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10061585-B2
Application numberUS-201615008850-A
CountryUS
Kind codeB2
Filing dateJan 28, 2016
Priority dateMar 14, 2013
Publication dateAug 28, 2018
Grant dateAug 28, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer program product for executing a machine instruction, the computer program product comprising: a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation; and a register field to be used to identify a register, the register to specify a location in memory of a first operand and another register field to be used to identify another register, the other register to specify a location in memory of the second operand; executing the machine instruction, the executing comprising: obtaining a modifier field associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number generate operation, the deterministic pseudorandom number generate operation comprising: for each block of memory of one or more blocks of memory of a first operand located using the machine instruction, generating a hash value using a selected hash technique and at least one seed value of a parameter block associated with the machine instruction; storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number; and updating, in a second register, a length of the first operand at the completion of the machine instruction, wherein the updating comprises incrementing or decrementing the length of the second register; executing the machine instruction another time, the executing the machine instruction another time comprising: based on the modifier field having a second value, performing a deterministic pseudorandom number seed operation, the deterministic pseudorandom number seed operation comprising: obtaining seed material based on information included in a second operand located using the machine instruction; using the selected hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in the parameter block associated with the machine instruction. 2. The computer program product of claim 1 , wherein the executing further comprises obtaining a function code associated with the machine instruction, the function code to specify a function to be performed, and based on the function code being a particular value, obtaining the modifier field. 3. The computer program product of claim 1 , wherein the parameter block is configured to include at least one of: a reseed counter to indicate a number of times the machine instruction has completed with a specific condition code since the parameter block was last instantiated or reseeded; a stream bytes field to track a number of bytes stored based on the generate operation; a value to indicate an internal state of a random number generator represented by the parameter block; or a constant value to be initialized by execution of a seed operation. 4. The computer program product of claim 1 , wherein the storing comprises storing right to left in the first operand. 5. The computer program product of claim 1 , wherein for a block of memory of the one or more blocks of memory, the generating the hash value comprises: adding a seed value of the at least one seed value of the parameter block and a block number of the block of memory being processed to provide a sum; combining the sum with padding to provide an input; and using the input and the selected hash technique to provide the generated hash value. 6. The computer program product of claim 5 , wherein the generating comprises generating the hash value for a number of blocks of memory, the number of blocks of memory determined based on a length of the first operand, and starting with a rightmost block of memory. 7. The computer program product of claim 1 , wherein the storing for one generated hash value comprises: determining whether a length of the first operand as indicated in a selected register of the machine instruction is a multiple of a defined number; based on the length being a multiple of the defined number, storing the one generated hash value in the corresponding block of memory of the first operand; and based on the length not being a multiple of the defined number, storing a portion of the one generated hash value in the corresponding block of memory of the first operand. 8. The computer program product of claim 7 , wherein the portion comprises a leftmost number of bytes of the one generated hash value. 9. The computer program product of claim 7 , wherein the method further comprises: based on the storing, adjusting the length of the first operand based on a number of bytes stored in the first operand; and updating a stream bytes field of the parameter block based on a number of bytes stored in the first operand. 10. The computer program product of claim 1 , wherein the selected hash technique comprises a 512 bit secure hash technique. 11. A computer system for executing a machine instruction, the computer system comprising: a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation; and a register field to be used to identify a register, the register to specify a location in memory of a first operand and another register field to be used to identify another register, the other register to specify a location in memory of the second operand; executing the machine instruction, the executing comprising: obtaining a modifier field associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number generate operation, the deterministic pseudorandom number generate operation comprising: for each block of memory of one or more blocks of memory of a first operand located using the machine instruction, generating a hash value using a selected hash technique and at least one seed value of a parameter block associated with the machine instruction; storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number; and updating, in a second register, a length of the first operand at the completion of the machine instruction, wherein the updating comprises incrementing or decrementing the length of the second register; executing the machine instruction another time, the executing the machine instruction another time comprising: based on the modifier field having a second value, performing a deterministic pseudorandom number seed operation, the deterministic pseudorandom number seed operation comprising: obtaining seed material based on information included in a second operand located using the machine instruction; using the selected hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in the parameter block associated with the machine instruction. 12. The computer system of claim 11 ,

Assignees

Inventors

Classifications

  • Random or pseudo-random number generators · CPC title

  • G06F7/582Primary

    Pseudo-random number generators · CPC title

  • Bit or string instructions · CPC title

  • involving random numbers or seeds · CPC title

  • Arithmetic instructions · CPC title

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Frequently asked questions

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What does patent US10061585B2 cover?
A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memor…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F7/582. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).