Frame buffer access tracking via a sliding window in a unified virtual memory system

Patent metadata

Field	Value
Publication number	US-10061526-B2
Application number	US-201615169532-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Mar 14, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.

First claim

What is claimed is:

1. A system, comprising:
a memory management unit that includes a sliding window tracker configured to:
detect a first access operation associated with a first memory page group included within a sliding window;
set a first reference bit corresponding to the first memory page group; and
based on a second reference bit corresponding to a second memory page group, cause a memory page in the second memory page group to migrate from a second memory to a first memory.

2. The system of claim 1 , wherein the second memory is partitioned into a plurality of memory page windows, each memory page window includes one or more memory page groups, and each reference corresponds to a different memory page group.

3. The system of claim 2 , wherein each of the memory page groups includes only one memory page.

4. The system of claim 2 , wherein each of the memory page groups includes only two memory pages.

5. The system of claim 2 , wherein each of the memory page groups includes a number of memory pages capable of being referenced by a single entry in a translation lookaside buffer.

6. The system of claim 1 , wherein the sliding window is defined based on a virtual base address stored in a window register and associated with the first memory page group.

7. The system of claim 6 , where in the sliding window tracker is further configured to perform one or more comparison operations between a virtual address associated with the first access operation and a plurality of bits associated with the window register to determine that the first access operation is associated with the sliding window.

8. The system of claim 1 , wherein the sliding window tracker is further configured to perform a plurality of write operations to set each reference bit to an inactive value prior to detecting the first access operation.

9. The system of claim 1 , wherein the sliding window tracker is further configured to locate the first reference bit within a reference vector based on a virtual address associated with the first access operation.

10. The system of claim 1 , wherein setting the first reference bit comprises setting the first reference bit to an active value, and causing the memory page in the second memory page group to migrate from the second memory to the first memory is in response to the active value of the first reference bit and an inactive value of the second reference bit.

11. A computer-implemented method for selecting memory pages to migrate to a first memory from a second memory in a unified virtual memory system, the method comprising:
detecting a first access operation associated with a first memory page group included within a sliding window;
performing a write operation to set a first reference bit corresponding to the first memory page group to an active value; and
in response to the active value of the first reference bit and an inactive value of a second reference bit corresponding to a second memory page group, causing a memory page in the second memory page group to migrate from the second memory to the first memory.

12. The method of claim 11 , wherein the second memory is partitioned into a plurality of memory page windows, each memory page window includes one or more memory page groups, and each reference corresponds to a different memory page group.

13. The method of claim 12 , wherein each of the memory page groups includes only one memory page.

14. The method of claim 12 , wherein each of the memory page groups includes only two memory pages.

15. The method of claim 12 , wherein each of the memory page groups includes a number of memory pages capable of being referenced by a single entry in a translation lookaside buffer.

16. The method of claim 12 , wherein the sliding window is defined based on a virtual base address stored in a window register and associated with the first memory page group.

17. The method of claim 16 , further comprising performing one or more comparison operations between a virtual address associated with the first access operation and a plurality of bits associated with the window register to determine that the first access operation is associated with the sliding window.

18. The method of claim 11 , further comprising performing a plurality of write operations to set each of the reference bits included in a reference vector to an inactive value prior to detecting the first access operation.

19. The method of claim 11 , further comprising locating the first reference bit within a reference vector based on a virtual address associated with the first access operation.

20. A computing device comprising:
a first processor;
a first memory associated with the first processor;
a second processor; and
a second memory associated with the second processor,
wherein the second processor includes a memory management unit that includes
a sliding window tracker configured to:
detect a first access operation associated with a first memory page group included within a sliding window;
set a first reference bit corresponding to the first memory page group to an active value; and
in response to an inactive value of a second reference bit corresponding to a second memory page group, cause a memory page in the second memory page group to migrate from a second memory to a first memory.

21. The computing device of claim 20 , wherein the second memory is partitioned into a plurality of memory page windows, each memory page window includes one or more memory page groups, and each reference corresponds to a different memory page group.

22. The computing device of claim 20 , wherein the second memory page group is also included within the sliding window.

23. The computing device of claim 20 , wherein causing the memory page in the second memory page group to migrate from the second memory to the first memory is further in response to the active value of the first reference bit.

Assignees

• Nvidia Corp

Inventors

• Mashey John
• Buschardt Cameron
• Deming James Leroy
• Duluk Jr Jerome F
• Fahs Brian

Classifications

• G06F2212/656

  Address space sharing · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0622 Primary

  in relation to access · CPC title