Electrical circuit odometer sensor array

Patent metadata

Field	Value
Publication number	US-10060974-B2
Application number	US-201414574746-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Approaches for detecting wear in integrated circuit chips are provided. An on-chip sensor system includes an integrated circuit chip including a plurality of sensor groups. Each respective one of the sensor groups is structured and arranged to detect a measure of wear corresponding to a respective one of a plurality of failure mechanisms.

First claim

What is claimed is:

1. An on-chip sensor system, comprising:
an integrated circuit chip comprising a plurality of sensor groups located on respective functional blocks of the integrated circuit chip, wherein output of the sensor groups correlates to actual wear of the integrated circuit chip based on an actual operational environment of the integrated circuit chip, the plurality of sensor groups including:
a first sensor group on a first functional block of the integrated circuit chip comprising first sensor structures that are configured to detect a measure of different amounts of wear based on a first failure mechanism; and
a second sensor group on a second functional block of the integrated circuit chip comprising second sensor structures that are configured to detect a measure of different amounts of wear based on a second failure mechanism different from the first failure mechanism.

2. The system of claim 1 , wherein each of the plurality of sensor groups are arranged in an array.

3. The system of claim 1 , wherein each of the first and second failure mechanisms comprise one of the group consisting of:
stress induced voids at a material-to-material interface;
stress induced shorting due to metal migration;
dielectric material breakdown; and
transistor failure.

4. The system of claim 1 , further comprising a monitoring core on the chip and operatively connected to each one of the plurality of sensor groups.

5. The system of claim 4 , wherein the monitoring core is configured to dynamically adjust operation of the chip based on a detected state of at least one of the plurality of sensor groups.

6. The system of claim 4 , wherein the monitoring core is configured to send a communication to an off-chip device based on a detected state of at least one of the plurality of sensor groups.

7. The system of claim 1 , wherein each of the first sensor structures comprises a metal via extending vertically between an upper metal wire and a lower metal wire.

8. The system of claim 1 , wherein:
a first one of the first sensor structures is structured and arranged to develop a void at an interface between a first via and a first wire based on a first level of exposure to the first failure mechanism;
a second one of the first sensor structures is structured and arranged to develop a void at an interface between a second via and a second wire based on a second level of exposure to the first failure mechanism; and
a third one of the first sensor structures is structured and arranged to develop a void at an interface between a third via and a third wire based on a third level of exposure to the first failure mechanism;
wherein the first level of exposure, the second level of exposure, and the third level of exposure are all different from one another.

9. The system of claim 1 , wherein each of the second sensor structures comprises a metal wire extending horizontally between two metal vias.

10. The system of claim 1 , wherein:
a first pair of the second sensor structures is structured and arranged to develop an electrical short based on a first level of exposure to the second failure mechanism;
a second pair of the second sensor structures is structured and arranged to develop an electrical short based on a second level of exposure to the second failure mechanism; and
a third pair of the second sensor structures is structured and arranged to develop an electrical short based on a third level of exposure to the second failure mechanism;
wherein the first level of exposure, the second level of exposure, and the third level of exposure are all different from one another.

11. The system of claim 1 , wherein:
there is a first spacing between a first one of the second sensor structures and a second one of the second sensor structures;
there is a second spacing between the second one of the second sensor structures and a third one of the second sensor structures;
there is a third spacing between the third one of the second sensor structures and a fourth one of the second sensor structures;
the second spacing is greater than the first spacing; and
the third spacing is greater than the second spacing.

12. The system of claim 1 , wherein:
the plurality of sensor groups further comprises a third sensor group comprising third sensor structures that are configured to indicate different amounts of wear based on a third failure mechanism, and a fourth sensor group comprising fourth sensor structures that are configured to indicate different amounts of wear based on a fourth failure mechanism; and wherein:
the first sensor group comprises thermo-mechanical stress sensors and the first failure mechanism comprises stress induced voids at a material-to-material interface;
the second sensor group comprises thermo-mechanical stress sensors and the second failure mechanism comprises stress induced shorting due to metal migration;
the third sensor group comprises thermo-mechanical stress and electromigration sensors, and the third failure mechanism comprises dielectric material breakdown; and
the fourth sensor group comprises transistor failure sensors and the fourth failure mechanism comprises accelerated transistor aging.

13. The system of claim 1 , wherein:
the chip additionally comprises an operational transistor that is separate from the plurality of sensor groups; and
one of the plurality of sensor groups comprises a stressed transistor that is operated at least one of a higher voltage, a higher temperature, and a higher frequency than the operational transistor.

14. The system of claim 1 , wherein the functional blocks are selected from the group consisting of: a processor core, a cache, an input/output block, a power region, and a nest.

15. A semiconductor device, comprising:
a first group of graduated sensor structures that are configured to fail sequentially at different levels of exposure to a first failure mechanism, the first group of graduated sensor structures on a first location in a die portion of an integrated circuit chip,
a second group of graduated sensor structures that are configured to fail sequentially at different levels of exposure to the first failure mechanism, the second group of graduated sensor structures on a second location in the die portion of the integrated circuit chip,
a third group of graduated sensor structures that are configured to fail sequentially at different levels of exposure to a second failure mechanism different from the first failure mechanism, the third group of graduated sensor structures on a third location in the die portion of the integrated circuit chip; and
a fourth group of graduated sensor structures that are configured to fail sequentially at different levels of exposure to the second failure mechanism, the fourth group of graduated sensor structures on a fourth location in the die portion of the integrated circuit chip,
wherein output of the first sensor group, the second sensor group, the third sensor group and the fourth sensor group correlates to an amount of actual wear the integrated circuit chip has experienced based on an actual operational environment of the integrated circuit chip.

16. The device of claim 15 , wherein:
the first group of graduated sensor structures comprises:
a first via between and contacting a first upper wire and a first lower wire, with a first junction at a first material-to-material interface between the first via and the first lower wire, the first junction having a first area defined by a distance between a vertical edge of the first lower wire and a vertical edge of the first via; and
a second

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Fry Jonathan R
• Klabes Christopher
• Martin Andrew J
• Mcgahay Vincent J
• Schlichting Kathryn E
• Smith Melissa A

Classifications

• G01C22/00 Primary

  Measuring distance traversed on the ground by vehicles, persons, animals or other moving solid bodies, e.g. using odometers, using pedometers · CPC title

• G01R31/2896 Primary

  Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title