Method and system for split voltage domain receiver circuits

Patent metadata

Field	Value
Publication number	US-10057091-B2
Application number	US-201715785066-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Oct 2, 2007
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.

First claim

What is claimed is:

1. A method for processing signals, the method comprising:
in an integrated circuit:
amplifying received electrical signals using stacked inverters, each in a plurality of partial voltage domains; and
combining said amplified received signals, utilizing a stacked cascode amplifier for each partial voltage domain, into a single differential signal in a single voltage domain, wherein each of said partial voltage domains is offset by a DC voltage from other of said partial voltage domains.

2. The method according to claim 1 , comprising receiving said electrical signals from a photodiode monitored in a complementary mode.

3. The method according to claim 2 , wherein said photodiode is integrated in said integrated circuit.

4. The method according to claim 1 , comprising combining said amplified received signals via stacked common source amplifiers.

5. The method according to claim 1 , comprising combining said amplified received signals via stacked common emitter amplifiers.

6. The method according to claim 1 , wherein said received electrical signals are DC coupled to said stacked inverters.

7. The method according to claim 1 , comprising DC coupling said amplified received signals prior to said combining.

8. The method according to claim 1 , comprising AC coupling said amplified received signals prior to said combining.

9. The method according to claim 1 , comprising amplifying and combining said received signals via cascode amplifiers.

10. The method according to claim 1 , wherein said voltage domains are stacked.

11. The method according to claim 10 , comprising controlling said stacked voltage domains via feedback loops.

12. A system for processing signals, the system comprising:
in an integrated circuit, one or more circuits operable to amplify received electrical signals using stacked inverters, each in a plurality of partial voltage domains; and
said one or more circuits being operable to combine said amplified received signals into a single differential signal in a single voltage domain utilizing a stacked cascode amplifier for each partial voltage domain wherein each of said partial voltage domains is offset by a DC voltage from other of said partial voltage domains.

13. The system according to claim 12 , wherein said one or more circuits are operable to receive said electrical signals from a photodiode monitored in a complementary mode.

14. The system according to claim 13 , wherein said photodiode is integrated in said integrated circuit.

15. The system according to claim 12 , wherein said one or more circuits are operable to combine said amplified received signals via stacked common source amplifiers.

16. The system according to claim 12 , wherein said one or more circuits combine said amplified received signals via stacked common emitter amplifiers.

17. The system according to claim 12 , wherein said received electrical signals are DC coupled to said stacked inverters.

18. The system according to claim 12 , wherein said one or more circuits are operable to DC couple said amplified received signals prior to said combining.

19. The system according to claim 12 , wherein said one or more circuits are operable to AC couple said amplified received signals prior to said combining.

20. The system according to claim 12 , wherein said one or more circuits are operable to amplify and combine said received signals via cascode amplifiers.

21. The system according to claim 12 , wherein said voltage domains are stacked.

22. The system according to claim 12 wherein said one or more circuits are operable to control said stacked voltage domains via feedback loops.

Assignees

• Luxtera Inc

Inventors

• Welch Brian

Classifications

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• G02B6/4201

  Packages, e.g. shape, construction, internal or external details · CPC title

• G02B6/4242

  Mounting of the optical light guide to the lid of the package · CPC title

• H04L25/061 Primary

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04B10/693

  Arrangements for optimizing the preamplifier in the receiver · CPC title