Continuous coarse-tuned phase locked loop

Patent metadata

Field	Value
Publication number	US-10056911-B2
Application number	US-201615385109-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Dec 21, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

First claim

What is claimed is:

1. A phase-locked loop (PLL) system, comprising:
a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal;
a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD;
multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal; and
a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals, the capacitance value and the first tuning signal affecting a frequency of the feedback signal;
wherein a frequency of an output signal of the VCO is adjusted by a varactor diode within the VCO.

2. The system of claim 1 , further comprising a low-pass filter coupled to the CP.

3. The system of claim 2 , wherein the low-pass filter comprises multiple capacitors and a resistor.

4. The system of claim 2 , wherein the low-pass filter comprises multiple capacitors and a switch.

5. The system of claim 4 , further comprising a logic NOR gate to control the switch, the NOR gate configured to receive the feedback signal and the phase-frequency reference signal as inputs.

6. The system of claim 1 , further comprising a comparator configured to receive the first tuning signal and the voltage reference signal as inputs.

7. The system of claim 6 , wherein the comparator produces a comparator output that controls multiple current sources in the multiple integrator cells.

8. The system of claim 7 , wherein alteration of the multiple current sources causes a change in the frequency of the feedback signal.

9. The system of claim 1 , wherein the multiple integrator cells cause the first tuning signal to remain within a predetermined voltage range.

10. The system of claim 1 , wherein each of the multiple integrator cells provides an output signal to control a corresponding transistor switch in the VCO, and wherein each corresponding transistor switch is configured to increase or decrease the capacitance value.

11. A phase-locked loop (PLL) system, comprising:
a comparator configured to receive a voltage reference signal and a tuning signal and to produce a comparator output;
a chain of integrator cells coupled to a plurality of transistor switches and configured to operate the plurality of transistor switches based on the comparator output; and
a voltage-controlled oscillator (VCO) comprising a varactor diode;
wherein a frequency of an output signal of the VCO is adjusted by the varactor diode.

12. The system of claim 11 , further comprising a filter, positioned between the comparator and a charge pump, that is configured to dampen a ripple associated with a PLL update.

13. The system of claim 11 , wherein the tuning signal maintains a voltage within a predetermined range of the voltage reference signal.

14. The system of claim 13 , wherein the voltage reference signal is within 10% of half of a voltage rail supply.

Assignees

• Texas Instruments Inc

Inventors

• Rombach Gerd

Classifications

• H03L7/103

  the additional signal being a digital signal · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title