Voltage mode driver with charge recycling

Patent metadata

Field	Value
Publication number	US-10056777-B2
Application number	US-201615192911-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A plurality of drivers for driving corresponding differential data output signals are arranged in series such that a first current discharged by a first one of the drivers is recycled through remaining ones of the drivers.

First claim

What is claimed is:

1. A data transmitter, comprising:
a power supply node configured to supply a power supply voltage;
a multiple-output linear dropout power regulator (multiple-output LDO) configured to charge a first intermediate voltage node to a first intermediate voltage that is less than the power supply voltage and to charge a second intermediate voltage node to a second intermediate voltage that is less than the first intermediate voltage;
a first driver coupled between the power supply node and the first intermediate voltage node, the first driver configured to source a first current out of a first output node responsive to a first binary state of a first differential data input signal, the first driver being further configured to discharge the first current from a second output node into the first intermediate voltage node responsive to the first binary state of the first differential data input signal;
a second driver coupled between the first intermediate voltage node and the second intermediate voltage node, wherein the second driver is configured to substantially receive the first current from the first intermediate voltage node and to source the first current out of a third output node responsive to a first binary state of a second differential data input signal, the second driver being further configured to discharge the first current from a fourth output node into the second intermediate voltage node responsive to the first binary state of the second differential data input signal; and
a third driver coupled between the second intermediate voltage node and ground, wherein the third driver is configured to substantially receive the first current from the second intermediate voltage node and to source the first current out of a fifth output node responsive to a first binary state of a third differential data input signal, the third driver being further configured to discharge the first current from a sixth output node into ground responsive to the first binary state of the third differential data input signal.

2. The data transmitter of claim 1 , wherein the first driver includes a first switch coupled between the first output node and the power supply node and includes a second switch coupled between the second output node and the first intermediate voltage node, and wherein the first switch and the second switch are both configured to close responsive to the first binary state of the first differential data input signal and configured to open responsive to a second binary state of the first differential data input signal.

3. The data transmitter of claim 2 , wherein the first switch comprises a first PMOS transistor and wherein the second switch comprises a second PMOS transistor.

4. The data transmitter of claim 2 , wherein the first driver further includes a first load resistor coupled between the first output node and the first switch and includes a second load resistor coupled between the second output node and the second switch.

5. The data transmitter of claim 2 , wherein the first driver further includes a third switch coupled between the second output node and the power supply node and a fourth switch coupled between the first output node and the first intermediate voltage node, wherein the third switch and the fourth switch are both configured to close responsive to the second binary state of the first differential data input signal and to open responsive to the first binary state of the first differential data input signal.

6. The data transmitter of claim 5 , wherein the third switch comprises a first PMOS transistor and wherein the fourth switch comprises a second PMOS transistor.

7. The data transmitter of claim 1 , wherein the multiple-output LDO is configured to respond to a feedback voltage and to a reference voltage to maintain the first intermediate voltage equal to two-thirds of the power supply voltage.

8. The data transmitter of claim 7 , wherein the multiple-output LDO comprises a differential amplifier configured to amplify a difference between the feedback voltage and the reference voltage to output the first intermediate voltage.

9. The data transmitter of claim 8 , wherein the reference voltage equals five-sixths of the power supply voltage.

10. The data transmitter of claim 1 , wherein the second driver comprises a plurality of transmission gates and wherein the third driver comprises a plurality of NMOS transistor switches.

11. The data transmitter of claim 10 , wherein the multiple-output LDO comprises:
a first single-output LDO including a first differential amplifier configured to drive a gate of a first NMOS transistor to produce the first intermediate voltage at a drain of the first NMOS transistor,
a second single-output LDO including a second differential amplifier configured to drive a gate of a first PMOS transistor to produce the second intermediate voltage at a drain of the first PMOS transistor; and
a third single-output LDO configured to charge the source of the first NMOS transistor and the source of the first PMOS transistor to a third intermediate voltage that is greater than the second intermediate voltage and less than the first intermediate voltage.

12. The data transmitter of claim 11 , wherein the third single-output LDO is configured to charge the source of the first PMOS transistor and the source of the first NMOS transistor to one-half the power supply voltage.

13. A data transmission method, comprising:
charging a first voltage node with a multiple-output linear dropout power regulator (multiple-output LDO) to a first intermediate voltage;
responsive to a first binary state of a first differential data input signal, coupling a first output node for a first driver to a power supply node charged to a power supply voltage while sourcing a first current from the first output node and coupling a second output node for the first driver to the first voltage node while sinking the first current from the second output node into the first voltage node, wherein the power supply voltage is greater than the first intermediate voltage;
charging a second voltage node with the multiple-output LDO to a second intermediate voltage, wherein the first intermediate voltage is greater than the second intermediate voltage, and wherein the second intermediate voltage is greater than ground;
responsive to a first binary state of a second differential data input signal, coupling a third output node for a second driver to the first voltage node while sourcing a second current from the third output node and coupling a fourth output node for the second driver to the a second voltage node while sinking the second current from the fourth output node into the second voltage node, wherein the second current is substantially equal to the first current; and
responsive to a first binary state of a third differential data input signal, coupling a fifth output node for a third driver to the second voltage node while sourcing a third current from the fifth output node and coupling a sixth output node for the third driver to ground while sinking the third current from the sixth output node into ground, wherein the third current is substantially equal to the second current.

14. The data transmission method of claim 13 , further comprising:
responsive to a second binary state of the first differential data input signal, coupling the second output node for the first driver to the power supply node while sourcing the first current from the second output node and coupling the first output node for the first driver to the first voltage node while sinking the first current from the first output node into the first

Assignees

• Qualcomm Inc

Inventors

• Kong Xiaohua
• Xu Jie

Classifications

• H04L25/00

  Baseband systems · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H02J7/0072 Primary

  Electricity · mapped topic

• H02J3/14

  by switching loads on to, or off from, the networks, e.g. progressively balanced loading · CPC title