Systems and methods for managing a voltage regulator

Patent metadata

Field	Value
Publication number	US-10056754-B2
Application number	US-201615054814-A
Country	US
Kind code	B2
Filing date	Feb 26, 2016
Priority date	Oct 22, 2013
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A voltage regulator may comprise a high-side switch and a low-side switch for delivering electrical current to the at least one information handling resource, a high-side driver configured to drive a high-side driving voltage for regulating a first electrical current of the high-side switch, a low-side driver configured to drive a low-side driving voltage for regulating a second electrical current of the low-side switch, and a control circuit configured to operate the at least one voltage regulator in both of a fixed dead time mode and an adaptive dead time mode.

First claim

What is claimed is:

1. An information handling system comprising:
at least one information handling resource;
at least one voltage regulator coupled to the at least one information handling resource and comprising:
a high-side switch and a low-side switch for delivering electrical current to the at least one information handling resource;
a high-side driver configured to drive a high-side driving voltage for regulating a first electrical current of the high-side switch;
a low-side driver configured to drive a low-side driving voltage for regulating a second electrical current of the low-side switch; and
a control circuit configured to operate the at least one voltage regulator in both of a fixed dead time mode and an adaptive dead time mode, wherein:
in the fixed dead time mode, the control circuit delays by a fixed amount a propagation of a transition of a pulse-width modulated input signal to at least one of the high-side driver and the low-side driver;
in the adaptive dead time mode, the control circuit transitions one of the high-side driving voltage and the low-side driving voltage in response to a determination that the other of the high-side driving voltage and the low-side driving voltage has decreased below a predetermined threshold voltage; and
the control circuit operates in the adaptive dead time mode in response to the at least one voltage regulator being disabled for at least a predetermined duration of time.

2. The information handling system of claim 1 , wherein the control circuit is further configured to operate in the adaptive dead time mode in response to the pulse-width modulated input signal operating at an intermediate voltage between a logic 1 voltage and a logic 0 voltage for at least a predetermined duration of time.

3. The information handling system of claim 1 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to a voltage supply of the high-side driver exceeding a pre-determined threshold voltage.

4. The information handling system of claim 1 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to the at least one voltage regulator operating in the adaptive dead time mode for at least a predetermined duration of time.

5. The information handling system of claim 1 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to the pulse-width modulated input signal operating at an active voltage corresponding to either of a logic 1 voltage and a logic 0 voltage.

6. A method comprising:
selecting a mode of operation of a voltage regulator from a fixed dead time mode and an adaptive dead time mode;
in the fixed dead time mode, delaying by a fixed amount a propagation of a transition of a pulse-width modulated input signal to at least one of a high-side driver and a low-side driver of the voltage regulator, wherein the high-side driver is configured to drive a high-side driving voltage for regulating a first electrical current delivered by a high-side switch to a load and the low-side driver is configured to drive a low-side driving voltage for regulating a second electrical current delivered by a low-side switch to the load;
operating in the adaptive dead time mode in response to the voltage regulator being disabled for at least a predetermined duration of time; and
in the adaptive dead time mode, transitioning one of the high-side driving voltage and the low-side driving voltage in response to a determination that the other of the high-side driving voltage and the low-side driving voltage has decreased below a predetermined threshold voltage.

7. The method of claim 6 , further comprising operating in the adaptive dead time mode in response to the pulse-width modulated input signal operating at an intermediate voltage between a logic 1 voltage and a logic 0 voltage for at least a predetermined duration of time.

8. The method of claim 6 , further comprising operating in the fixed dead time mode in response to a voltage supply of the high-side driver exceeding a pre-determined threshold voltage.

9. The method of claim 6 , further comprising operating in the fixed dead time mode in response to operating in the adaptive dead time mode for at least a predetermined duration of time.

10. The method of claim 6 , further comprising operating in the fixed dead time mode in response to the pulse-width modulated input signal operating at an active voltage corresponding to either of a logic 1 voltage and a logic 0 voltage.

11. A voltage regulator comprising:
a high-side switch and a low-side switch for delivering electrical current to a load;
a high-side driver configured to drive a high-side driving voltage for regulating a first electrical current of the high-side switch;
a low-side driver configured to drive a low-side driving voltage for regulating a second electrical current of the low-side switch; and
a control circuit configured to operate the voltage regulator in both of a fixed dead time mode and an adaptive dead time mode, wherein:
in the fixed dead time mode, the control circuit delays by a fixed amount a propagation of a transition of a pulse-width modulated input signal to at least one of the high-side driver and the low-side driver;
in the adaptive dead time mode, the control circuit transitions one of the high-side driving voltage and the low-side driving voltage in response to a determination that the other of the high-side driving voltage and the low-side driving voltage has decreased below a predetermined threshold voltage; and
the control circuit is configured to operate in the adaptive dead time mode in response to the voltage regulator being disabled for at least a predetermined duration of time.

12. The voltage regulator of claim 11 , wherein the control circuit is further configured to operate in the adaptive dead time mode in response to the pulse-width modulated input signal operating at an intermediate voltage between a logic 1 voltage and a logic 0 voltage for at least a predetermined duration of time.

13. The voltage regulator of claim 11 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to a voltage supply of the high-side driver exceeding a pre-determined threshold voltage.

14. The voltage regulator of claim 11 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to the voltage regulator operating in the adaptive dead time mode for at least a predetermined duration of time.

15. The voltage regulator of claim 11 , wherein the control circuit is further configured to operate in the fixed dead time mode in response to the pulse-width modulated input signal operating at an active voltage corresponding to either of a logic 1 voltage and a logic 0 voltage.

Assignees

• Dell Products Lp

Inventors

• Zhang Kejiu
• Luo Shiguo
• Li Hang

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title

• H02J1/00 Primary

  Circuit arrangements for DC mains or DC distribution networks · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title