Method for manufacturing vertical super junction drift layer of power semiconductor devices

Patent metadata

Field	Value
Publication number	US-10056452-B2
Application number	US-201615197701-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Dec 30, 2013
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H + ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

First claim

The invention claimed is:

1. A method for manufacturing a vertical super junction drift layer for power semiconductor devices, the method comprising:
a): using a P+ single crystal silicon to prepare a P+ substrate;
b1: forming a P-type region through epitaxial growth on the P+ substrate;
b2: forming an N-type region through epitaxial growth on the P-type region;
b3: growing a field oxide layer on the N-type region;
b4: etching an active area in the N-type region;
b5: growing a gate oxide on the N-type region;
b6: depositing and etching polysilicon on the gate oxide;
b7: implanting boron ions in the N-type region and then performing a drive-in to form a P-body base region;
b8: implanting arsenic ions in the P-body base region and then performing a drive-in to form an N + source region;
b9: depositing boro-phospho-silicate-glass (BPSG) on the P-body base region and then reflowing the BPSG;
b10: etching contact holes on the P-body base region;
b11: implanting boron ions in the P-body base region and then annealing to form a P+ contact region; and
b12: metallizing a top surface of the P+ substrate and forming an emitter on the BPSG;
c): thinning a back surface of the P+ single crystal silicon;
d): selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly, and then annealing to form N pillars in the P-type region; and
e): metallizing the back surface of the P+ single crystal silicon.

2. The method of claim 1 , wherein d) further comprises: selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly and annealing to form the N pillars in the P-type region, and repeating implanting H + ions and then annealing to form an N-Field stop layer between the P+ substrate and the N pillars.

3. A method for manufacturing a vertical super junction drift layer of power semiconductor devices, the method comprising:
a): using a P+ single crystal silicon to prepare a P+ substrate;
b1: forming an N-Field stop layer through epitaxial growth on the P+ substrate;
b2: forming a P-type region through epitaxial growth on the N-Field stop layer;
b3: forming an N-type region through epitaxial growth on the P-type region;
b4: growing a field oxide layer on N-type region;
b5: etching an active area in the N-type region;
b6: growing a gate oxide on the N-type region;
b7: depositing and etching polysilicon on the gate oxide;
b8: implanting boron ions in N-type region and then performing a drive-in to form a P-body base region;
b9: implanting arsenic ions in the P-body base region and then performing a drive-in to form an N + source region;
b10: depositing BPSG on the P-body base region and then reflowing the BPSG;
b11: etching contact holes on the P-body base region;
b12: implanting boron ions in the P-body base region and then annealing to form a P+ contact region; and
b13: metallizing a top surface of the P+ substrate and forming an emitter on the BPSG;
c): thinning a back surface of the P+ single crystal silicon;
d): selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly, and then annealing to form N pillars in the P-type region; and
e): metallizing the back surface of the P+ single crystal silicon.

4. A method for manufacturing a vertical super junction drift layer for power semiconductor devices, the method comprising:
a): using a P+ single crystal silicon to prepare a P+ substrate;
b1: forming a P-type region through epitaxial growth on the P+ substrate;
b2: implanting phosphorus ions or arsenic ions at a top surface of the P-type region and then performing a drive-in to form an N-type region in the P-type region;
b3: growing a field oxide layer on the N-type region;
b4: etching an active area in the N-type region;
b5: growing a gate oxide on the N-type region;
b6: depositing and etching polysilicon on the gate oxide;
b7: implanting boron ions in N-type region and then performing a drive-in to form a P-body base region;
b8: implanting arsenic ions in the P-body base region and then performing a drive-in to form an N + source region;
b9: depositing BPSG on the P-body base region and then reflowing the BPSG;
b10: etching contact holes on the P-body base region;
b11: implanting boron ions in the P-body base region and then annealing to form a P+ contact region; and
b12: metallizing a top surface of the P+ substrate and forming an emitter on the BPSG;
c): thinning a back surface of the P+ single crystal silicon;
d): selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly, and then annealing to form N pillars in the P-type region; and
e): metallizing the back surface of the P+ single crystal silicon.

5. The method of claim 4 , wherein d) further comprises: selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly and annealing to form the N pillars in the P-type region, and repeating implanting H + ions and then annealing to form an N-Field stop layer between the P+ substrate and the N pillars.

6. A method for manufacturing a vertical super junction drift layer for power semiconductor devices, the method comprising:
a): using a P+ single crystal silicon to prepare a P+ substrate;
b1: forming an N-Field stop layer through epitaxial growth on the P+ substrate;
b2: forming a P-type region through epitaxial growth on the N-Field stop layer;
b3: implanting phosphorus ions or arsenic ions at a top surface of the P-type region and then performing a drive-in to form an N-type region in the P-type region;
b4: growing a field oxide layer on the N-type region;
b5: etching an active area in the N-type region;
b6: growing a gate oxide on the N-type region;
b7: depositing and etching polysilicon on the gate oxide;
b8: implanting boron ions in N-type region and then performing a drive-in to form a P-body base region;
b9: implanting arsenic ions in the P-body base region and then performing a drive-in to form an N + source region;
b10: depositing BPSG on the P-body base region and then reflowing the BPSG;
b11: etching contact holes on the P-body base region;
b12: implanting boron ions in the P-body base region and then annealing to form a P+ contact region; and
b13: metallizing a top surface of the P+ substrate and forming an emitter on the BPSG;
c): thinning a back surface of the P+ single crystal silicon;
d): selectively implanting H + ions at the back surface of the P+ single crystal silicon repeatedly, and then annealing to form N pillars in the P-type region; and
e): metallizing the back surface of the P+ single crystal silicon.

Assignees

• Univ Electronic Sci & Tech China
• Electronic And Information Eng In Dongguan Uestc

Inventors

• Li Zehong
• Song Wenlong
• Song Xunyi
• Gu Hongming
• Zou Youbiao
• Zhang Jinping
• Zhang Bo

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P34/40

  with high-energy radiation · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title