Limiting electronic package warpage

US10056268B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10056268-B2
Application numberUS-201715792803-A
CountryUS
Kind codeB2
Filing dateOct 25, 2017
Priority dateMay 28, 2015
Publication dateAug 21, 2018
Grant dateAug 21, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.

First claim

Opening claim text (preview).

The invention claimed is: 1. A electronic package comprising: a carrier comprising a top surface and a bottom surface configured to be electrically connected to a system board; a semiconductor chip electrically connected to the top surface of the carrier; a lid attached to the top surface of the carrier that encloses semiconductor chip, the lid comprising a perimeter recess within the upper half of the lid, the perimeter recess comprising a horizontal recess and vertical recess comprising two recess sidewalls; and a lid-ring attached to the lid within the perimeter recess, the lid ring comprising a horizontal portion orthogonal and distally connected to a vertical portion, wherein the horizontal portion comprises a greater width than height, is parallel with the semiconductor chip, and is juxtaposed within the horizontal recess, wherein the vertical portion comprises a greater height than width and is juxtaposed between the two vertical recess sidewalls, wherein a perimeter sidewall of the lid-ring horizontal portion is coplanar with a perimeter sidewall of the lid, and wherein the lid-ring applies a contracting force against the upper half of the lid to exert a reverse bending moment upon the lid. 2. The electronic package of claim 1 , wherein the lid is in thermal contact with the semiconductor chip. 3. The electronic package of claim 1 , wherein a top surface of the lid and a top surface the lid-ring are coplanar. 4. The electronic package of claim 1 , wherein the lid and the lid-ring are the same material. 5. The electronic package of claim 1 , wherein the lid is fabricated from copper and the lid-ring is fabricated from aluminum. 6. The electronic package of claim 1 , further comprising: a heat sink thermally attached to a top surface of the lid. 7. The electronic package of claim 6 , wherein the heat sink is further thermally attached to a top surface of the lid ring. 8. A electronic device comprising: a carrier comprising a top surface and a bottom surface configured to be electrically connected to a system board; a semiconductor chip electrically connected to the top surface of the carrier; a lid attached to the top surface of the carrier that encloses semiconductor chip, the lid comprising a perimeter recess within the upper half of the lid, the perimeter recess comprising a horizontal recess and vertical recess comprising two recess sidewalls; and a lid-ring attached to the lid within the perimeter recess, the lid ring comprising a horizontal portion orthogonal and distally connected to a vertical portion, wherein the horizontal portion comprises a greater width than height, is parallel with the semiconductor chip, and is juxtaposed within the horizontal recess, wherein the vertical portion comprises a greater height than width and is juxtaposed between the two vertical recess sidewalls, wherein a perimeter sidewall of the lid-ring horizontal portion is coplanar with a perimeter sidewall of the lid, and wherein the lid-ring applies a contracting force against the upper half of the lid to exert a reverse bending moment upon the lid. 9. The electronic device of claim 8 , wherein the lid is in thermal contact with the semiconductor chip. 10. The electronic device of claim 8 , wherein a top surface of the lid and a top surface the lid-ring are coplanar. 11. The electronic device of claim 8 , wherein the lid and the lid-ring are the same material. 12. The electronic device of claim 8 , wherein the lid is fabricated from copper and the lid-ring is fabricated from aluminum. 13. The electronic device of claim 8 , further comprising: a heat sink thermally attached to a top surface of the lid. 14. The electronic device of claim 13 , wherein the heat sink is further thermally attached to a top surface of the lid ring.

Assignees

Inventors

Classifications

  • characterised by their materials · CPC title

  • characterised by their materials · CPC title

  • of die-attach connectors · CPC title

  • of bump connectors · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

Patent family

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External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10056268B2 cover?
An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W76/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 21 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).