Nonvolatile memory device including multi-plane structure

Patent metadata

Field	Value
Publication number	US-10056148-B2
Application number	US-201615342027-A
Country	US
Kind code	B2
Filing date	Nov 2, 2016
Priority date	Nov 12, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including a first plane and a second plane; and
an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select lines and configured to provide a string select signal and a string unselect signal to the first and second string select lines, wherein:
the address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes,
memory cells of the first and second planes are selectively accessed in accordance with signals applied to word lines, bit lines, and ground selection lines, and
the first and second planes do not share any of the word lines, bit lines, and ground selection lines.

2. The nonvolatile memory device as set forth in claim 1 , wherein:
the address decoder includes a string select line selection circuit configured to provide the string select signal and the string unselect signal to each of the first and second planes, and
the string select line selection circuit includes a first string switch configured to control the first string select lines according to a first string select line address and a second string switch configured to control the second string select lines according to a second string select line address.

3. The nonvolatile memory device as set forth in claim 2 , wherein:
the address decoder includes a switch controller configured to store the first and second string selection addresses, and
the switch controller extracts the first and second string select line addresses from externally received addresses and includes a first address storage unit configured to store the first string select line address and a second address storage unit configured to store the second string select line address.

4. The nonvolatile memory device as set forth in claim 1 , wherein:
the address decoder includes a switch controller configured to store the different string select line addresses, and
the switch controller includes a first stage storage unit configured to store first and second string select line addresses, each corresponding to a string select line to which the string select signal is to be applied currently, and a second stage storage unit configured to store third and fourth string select line addresses, each corresponding to a string select line to which the string select signal is to be applied next.

5. The nonvolatile memory device as set forth in claim 4 , wherein:
the first and third string select line addresses correspond to the first plane, and
the second and fourth string select line addresses correspond to the second plane.

6. The nonvolatile memory device as set forth in claim 4 , wherein:
the address decoder includes a string select line selection circuit configured to provide the string select signal and the string unselect signal to each of the first and second planes, and
the string select line selection circuit includes a first string switch configured to control the first string select lines according to a first string select line address and a second string switch configured to control the second string select lines according to a second string select line address.

7. The nonvolatile memory device as set forth in claim 4 , wherein the first stage storage unit stores the third and fourth string select line addresses after the address decoder provides the string select signal and the string unselect signal to each of the first and second planes.

8. A nonvolatile memory device comprising:
a memory cell array including a plurality of planes; and
an address decoder connected to each of the planes through a plurality of string select lines and configured to provide a string select signal and a string unselect signal to each of the planes, wherein:
the address decoder divides the planes into a plurality of groups and independently provides the string select signal and the string unselect signal based on a different string select line address corresponding to each of the groups,
memory cells of the planes are selectively accessed in accordance with signals applied to word lines, bit lines, and ground selection lines, and
the planes do not share any of the word lines, bit lines, and ground selection lines.

9. The nonvolatile memory device as set forth in claim 8 , wherein each of the groups includes at least one plane.

10. The nonvolatile memory device as set forth in claim 8 , wherein:
the address decoder includes a switch controller configured to store the different string select line addresses, and
the switch controller extracts first and second string select line addresses from externally received addresses and includes a first address storage unit configured to store the first string select line address and a second address storage unit configured to store the second string select line address.

11. The nonvolatile memory device as set forth in claim 10 , wherein:
the address decoder includes a string select line selection circuit configured to provide the string select signal and the string unselect signal to each of the planes, and
the string select line selection circuit includes a first string switch configured to control a first plane, a second string switch configured to control a second plane, and a third string switch configured to control a third plane.

12. The nonvolatile memory device as set forth in claim 11 , wherein:
the first and second planes belong to a first group and are respectively controlled by the first and second string switches according to the first string select line address, and
the third plane belongs to a second group and is controlled by the third string switch according to the second string select line address.

13. The nonvolatile memory device as set forth in claim 11 , wherein the string select line selection circuit further includes a fourth string switch configured to control a fourth plane.

14. The nonvolatile memory device as set forth in claim 13 , wherein:
the first and second planes belong to a first group and are respectively controlled by the first and second string switches according to the first string select line address, and
the third and fourth planes belong to a second group and are respectively controlled by the third and fourth switches according to the second string select line address.

15. The nonvolatile memory device as set forth in claim 8 , wherein:
the address decoder includes a switch controller configured to store the different string select line addresses,
the switch controller includes a first stage storage unit configured to store first and second string select line addresses, each corresponding to a string select line to which the string select line signal is to be applied currently, and a second stage storage unit configured to store third and fourth string select line addresses, each corresponding to a string select line to which the string select signal is to be applied next, and
the first and third string select line addresses correspond to a first group and the second and fourth string select line addresses correspond to a second group.

16. A nonvolatile memory device comprising:
a memory cell array comprising a first plane of first memory cell strings and a second plane of second memory cell strings, each of the first and second memory cell strings comprising a plurality of memory cells connected electrically in series,

Assignees

• Kwak Donghun
• Byeon Daeseok
• Yoon Chiweon
• Samsung Electronics Co Ltd

Inventors

• Kwak Donghun
• Byeon Daeseok
• Yoon Chiweon

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/04 Primary

  using variable threshold transistors, e.g. FAMOS · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title