Correlated electron switch programmable fabric

Patent metadata

Field	Value
Publication number	US-10056143-B2
Application number	US-201514848129-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Sep 8, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

First claim

What is claimed is:

1. An apparatus, comprising: a programmable fabric comprising:
a plurality of metallization layers; and
a first plurality of correlated electron switch devices to be positioned between a first metallization layer of the plurality of metallization layers and a second metallization layer of the plurality of metallization layers, and a second plurality of correlated electron switch devices to be positioned between the second metallization layer and a third metallization layer of the plurality of metallization layers, wherein the first and second pluralities of correlated electron switch devices are programmable to selectively open or close one or more of a plurality of conductive paths between one or more of a first plurality of electrically conductive lines formed on the first metallization layer and one or more of a second plurality of electrically conductive lines formed on the third metallization layer, and wherein opening or closing the one or more of the plurality of conductive paths connects or disconnects portions of an integrated circuit.

2. The apparatus of claim 1 , wherein the programmable fabric further comprising a cross-point array, wherein the first plurality of electrically conductive lines are oriented approximately parallel with each other, wherein the second electrically conductive lines are oriented approximately parallel with each other, and wherein the first electrically conductive lines are oriented approximately orthogonally to the second electrically conductive lines.

3. The apparatus of claim 2 , wherein one or more of the first plurality of correlated electron switch devices are to be individually positioned at one or more intersections of the first electrically conductive lines and the second electrically conductive lines of the second metallization layer.

4. The apparatus of claim 3 , wherein the programmable fabric further to comprise one or more access devices to be respectively positioned at the one or more intersections of the first electrically conductive lines and the second electrically conductive lines.

5. The apparatus of claim 4 , wherein the one or more access devices to comprise schottky diodes.

6. The apparatus of claim 3 , further comprising a voltage and/or current source, wherein to transition a particular correlated electron switch device of the first plurality of correlated electron switch devices from a first impedance state to a second impedance state, the voltage and/or current source to apply a programming voltage across a particular electrically conductive line of a particular metallization layer and a particular electrically conductive line of another particular metallization layer.

7. The apparatus of claim 1 , wherein one or more of the first and second pluralities of correlated electron switch devices to have particular programmable impedance characteristics to include particular programmable resistance and capacitance characteristics.

8. A memory device, comprising:
a plurality of correlated electron switch devices to be positioned within a three-dimensional cross-point array, wherein the three-dimensional cross-point array to comprise a plurality of layers of electrically conductive lines including a first layer, a second layer, and a third layer, wherein one or more of the plurality of correlated electron switch devices are to be positioned between the first and second layers of the electrically conductive lines and wherein another one or more of the plurality of correlated electron switch devices are to be positioned between the second and third layers of the electrically conductive lines to provide a plurality of programmable electrically conductive paths between the plurality of layers of electrically conductive lines and one or more other of the plurality of layers of electrically conductive lines, wherein one or more of the plurality of correlated electron switch devices to have particular programmable impedance characteristics to include particular programmable resistance and capacitance characteristics.

9. The memory device of claim 8 , wherein one or more of the plurality of correlated electron switch devices are to be individually positioned at one or more intersections of approximately orthogonally positioned electrically conductive lines.

10. The memory device of claim 9 , wherein the plurality of correlated electron switch devices are to be individually addressable within the three-dimensional cross-point array through selection of a particular pair of approximately orthogonally positioned electrically conductive lines.

11. The memory device of claim 9 , further comprising a voltage and/or current source, wherein the approximately orthogonally positioned electrically conductive lines to comprise a plurality of bit lines and at least one word line.

12. The memory device of claim 11 , wherein to program a particular correlated electron switch device within the three-dimensional cross-point array, the voltage and/or current source to apply a programming voltage across a particular word line and a particular bit line.

13. The memory device of claim 11 , wherein to detect an impedance state of a specified plurality of correlated electron switch devices within the three-dimensional cross-point array, the voltage and/or current source to apply a read voltage across one or more specified word lines and a plurality of specified bit lines.

14. The memory device of claim 8 , further comprising one or more access devices to be positioned with one or more respective correlated electron switch devices at one or more intersections of the approximately orthogonally positioned electrically conductive lines.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shifren Lucian
• Yeric Greg
• Sinha Saurabh
• Cline Brian
• Chandra Vikas

Classifications

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H01L45/04

  Electricity · mapped topic