Circuit device, physical quantity detection device, electronic apparatus, and moving object

Patent metadata

Field	Value
Publication number	US-10055975-B2
Application number	US-201615143849-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	May 14, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A circuit device includes a synchronization detection circuit which performs synchronization detection of a physical quantity signal of an input signal and outputs the physical quantity signal, and a filter unit. The synchronization detection circuit includes first and second detection circuits, and the filter unit includes first and second filters. In a first mode, the physical quantity signal from the first detection circuit is input to the first filter, and the undesired signal from the second detection circuit is input to the second filter. In a second mode, the physical quantity signal from the first detection circuit is input to the first filter and the second filter.

First claim

What is claimed is:

1. A circuit device comprising:
a synchronization detection circuit which receives an input signal including a physical quantity signal and an undesired signal, performs synchronization detection of the physical quantity signal from the input signal, and outputs the physical quantity signal; and
a filter unit which is provided on a rear stage side of the synchronization detection circuit,
wherein the synchronization detection circuit includes
a first detection circuit which receives the input signal; and
a second detection circuit which receives the input signal,

wherein the filter unit includes
a first filter; and
a second filter,

wherein the first detection circuit performs synchronization detection of the physical quantity signal from the input signal based on a first clock signal and outputs the physical quantity signal,
wherein the second detection circuit performs synchronization detection of the undesired signal from the input signal based on a second clock signal having a phase different from a phase of the first clock signal and outputs the undesired signal,
wherein, in a first mode, the physical quantity signal from the first detection circuit is input to the first filter, and the undesired signal from the second detection circuit is input to the second filter, and
wherein, in a second mode, the physical quantity signal from the first detection circuit is input to the first filter and the second filter.

2. The circuit device according to claim 1 , further comprising:
a signal selection circuit which is provided between the synchronization detection circuit and the filter unit,
wherein, in the first mode, the signal selection circuit outputs the physical quantity signal from the first detection circuit to the first filter and outputs the undesired signal from the second detection circuit to the second filter, and
wherein, in the second mode, the signal selection circuit outputs the physical quantity signal from the first detection circuit to the first filter and the second filter.

3. The circuit device according to claim 1 , wherein a time period which is configured by a first time period that is set to the first mode and a second time period that is set to the second mode is repeated during a normal diagnosis period after the circuit device starts.

4. The circuit device according to claim 1 ,
wherein, in the first and second modes, the first detection circuit performs synchronization detection of the physical quantity signal from the input signal based on the first clock signal and outputs the physical quantity signal, and the second detection circuit performs synchronization detection of the undesired signal from the input signal based on the second clock signal and outputs the undesired signal,
wherein, in third and fourth modes, the first detection circuit performs synchronization detection of the undesired signal from the input signal based on the second clock signal and outputs the undesired signal, and the second detection circuit performs synchronization detection of the physical quantity signal from the input signal based on the first clock signal and outputs the physical quantity signal,
wherein, in the third mode, the undesired signal from the first detection circuit is input to the second filter, and the physical quantity signal from the second detection circuit is input to the first filter, and
wherein, in the fourth mode, the physical quantity signal from the second detection circuit is input to the first filter and the second filter.

5. The circuit device according to claim 4 , further comprising:
a signal selection circuit which is provided between the synchronization detection circuit and the filter unit,
wherein, in the first mode, the signal selection circuit outputs the physical quantity signal from the first detection circuit to the first filter and outputs the undesired signal from the second detection circuit to the second filter,
wherein, in the second mode, the signal selection circuit outputs the physical quantity signal from the first detection circuit to the first filter and the second filter,
wherein, in the third mode, the signal selection circuit outputs the undesired signal from the first detection circuit to the second filter and outputs the physical quantity signal from the second detection circuit to the first filter, and
wherein, in the fourth mode, the signal selection circuit outputs the physical quantity signal from the second detection circuit to the first filter and the second filter.

6. The circuit device according to claim 4 ,
wherein the first detection circuit receives a differential input signal which is configured by a positive input signal and a negative input signal as the input signal, and outputs a first differential output signal which is configured by a first positive output signal and a first negative output signal,
wherein the second detection circuit receives the differential input signal as the input signal, and outputs a second differential output signal which is configured by a second positive output signal and a second negative output signal,
wherein, in the first and second modes, the first detection circuit outputs the physical quantity signal as the first differential output signal, and the second detection circuit outputs the undesired signal as the second differential output signal, and
wherein, in the third and fourth modes, the first detection circuit outputs the undesired signal as the first differential output signal, and the second detection circuit outputs the physical quantity signal as the second differential output signal.

7. The circuit device according to claim 6 ,
wherein the first detection circuit includes
a first switch element which is provided between a positive input node of the positive input signal that configures the differential input signal and a first positive output node of the first positive output signal that configures the first differential output signal, is turned on or off based on the first clock signal in the first and second modes, and is turned on or off based on the second clock signal in the third and fourth modes;
a second switch element which is provided between a negative input node of the negative input signal that configures the differential input signal and a first negative output node of the first negative output signal that configures the first differential output signal, is turned on or off based on the first clock signal in the first and second modes, and is turned on or off based on the second clock signal in the third and fourth modes;
a third switch element which is provided between the negative input node and the first positive output node, is turned on or off based on a first inverted clock signal that is an inverted signal of the first clock signal in the first and second modes, and is turned on or off based on a second inverted clock signal that is an inverted signal of the second clock signal in the third and fourth modes; and
a fourth switch element which is provided between the positive input node and the first negative output node, is turned on or off based on the first inverted clock signal in the first and second modes, and is turned on or off based on the second inverted clock signal in the third and fourth modes, and

wherein the second detection circuit includes
a fifth switch element which is provided between the positive input node and a second positive output node of the second positive output signal that configures the second differential output signal, is turned on or off based on the second clock signal in the first and second modes, and is turned on or off based on the first clock signal in the third and fourth modes;
a sixth switch element which is provided between the nega

Assignees

• Seiko Epson Corp

Inventors

• Aoyama Takashi
• Seo Kentaro

Classifications

• G08C25/00

  Arrangements for preventing or correcting errors; Monitoring arrangements · CPC title

• H04J3/14

  Monitoring arrangements {(for SDH/SONET rings H04J3/085)} · CPC title

• H04J3/0658

  Clock or time synchronisation among packet nodes · CPC title

• G08C2200/00

  Transmission systems for measured values, control or similar signals · CPC title

• G08C15/06 Primary

  successively, i.e. using time division · CPC title