Dynamic clock lane assignment for increased performance and security

Patent metadata

Field	Value
Publication number	US-10055380-B2
Application number	US-201815862801-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Dec 14, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

First claim

What is claimed is:

1. A data handling system comprising:
a transmitter that transmits a signal pattern upon each lane of a multiple lane bus;
a receiver that receives the signal pattern from each lane of the multiple lane bus, determines a distortion associated with the received signal pattern from each lane, and identifies a particular lane of the multiple lane bus that is associated with a smallest distortion;
wherein the transmitter or the receiver assigns the particular lane associated with smallest distortion as a clock lane that transmits a reference clock signal between the transmitter and the receiver in subsequent signal transmissions between the transmitter and the receiver.

2. The data handling system of claim 1 , wherein the reference clock signal coordinates actions of a first digital circuit within the transmitter and a second digital circuit within the receiver.

3. The data handling system of claim 1 , wherein the receiver further generates a respective eye diagram of the received signal pattern from each lane.

4. The data handling system of claim 3 , wherein the receiver further measures a respective eye width of each eye diagram of the received signal pattern from each lane.

5. The data handling system of claim 4 , wherein the receiver identifies the particular lane associated with the smallest distortion as the lane associated with the widest eye width.

6. The data handling system of claim 4 , further comprising an additional lane than is necessary for the multiple lane bus to communicate a predetermined data width from the transmitter to the receiver.

7. The data handling system of claim 6 , wherein the receiver identifies a lane of the multiple lane bus associated with the narrowest eye width as an inactive lane that does not transmit signals from the transmitter to the receiver in subsequent signal communications from the transmitter to the receiver.

8. A data handling system comprising:
a transmitting processor that transmits a signal pattern upon each lane of a multiple lane bus;
a receiving processor that receives the signal pattern from each lane of the multiple lane bus, determines a distortion associated with the received signal pattern from each lane, and identifies a particular lane of the multiple lane bus that is associated with a smallest distortion;
wherein the transmitting processor or the receiving processor assigns the particular lane associated with smallest distortion as a clock lane that transmits a reference clock signal between the transmitting processor and the receiving processor in subsequent signal transmissions between the transmitting processor and the receiving processor.

9. The data handling system of claim 8 , wherein the reference clock signal coordinates actions of a first digital circuit within the transmitting processor and a second digital circuit within the receiving processor.

10. The data handling system of claim 8 , wherein the receiving processor further generates a respective eye diagram of the received signal pattern from each lane.

11. The data handling system of claim 10 , wherein the receiving processor further measures a respective eye width of each eye diagram of the received signal pattern from each lane.

12. The data handling system of claim 11 , wherein the receiving processor identifies the particular lane associated with the smallest distortion as the lane associated with the widest eye width.

13. The data handling system of claim 11 , further comprising an additional lane than is necessary for the multiple lane bus to communicate a predetermined data width from the transmitting processor to the receiving processor.

14. The data handling system of claim 13 , wherein the receiving processor identifies a lane of the multiple lane bus associated with the narrowest eye width as an inactive lane that does not transmit signals from the transmitting processor to the receiving processor in subsequent signal communications from the transmitting processor to the receiving processor.

15. A system comprising a first processor communicatively connected to a second processor by a multiple lane bus, the first processor comprising a first computer readable storage medium and the second processor comprising a second computer readable storage medium, the first computer readable storage medium and the second computer readable storage medium collectively comprising program instructions that are readable to cause:
the first processor to transmit a signal pattern upon each lane of a multiple lane bus;
the second processor to receive the signal pattern from each lane of the multiple lane bus, determine a distortion associated with the received signal pattern from each lane, and identify a particular lane of the multiple lane bus that is associated with a smallest distortion; and
the first processor or the second processor to assign the particular lane associated with smallest distortion as a clock lane that transmits a reference clock signal between the first processor and the second processor in subsequent signal transmissions between the first processor and the second processor.

16. The system of claim 15 , wherein the reference clock signal coordinates actions of a first digital circuit within the first processor and a second digital circuit within the second processor.

17. The system of claim 15 , wherein the second processor further generates a respective eye diagram of the received signal pattern from each lane.

18. The system of claim 17 , wherein the second processor further measures a respective eye width of each eye diagram of the received signal pattern from each lane.

19. The system of claim 18 , wherein the second processor identifies the particular lane associated with the smallest distortion as the lane associated with the widest eye width.

20. The system of claim 15 , further comprising an additional lane than is necessary for the multiple lane bus to communicate a predetermined data width from the first processor to the second processor.

Assignees

• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Doyle Matthew S
• Jeanson Mark J
• Maxson Mark O

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4018

  with data-width conversion · CPC title

• G06F11/1428

  with loss of hardware functionality · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title