Apparatus and method for shared least recently used (LRU) policy between multiple cache levels

Patent metadata

Field	Value
Publication number	US-10055360-B2
Application number	US-201514975752-A
Country	US
Kind code	B2
Filing date	Dec 19, 2015
Priority date	Dec 19, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

First claim

What is claimed is:

1. An apparatus comprising:
a level N cache configured to store a first plurality of entries; and
a level N+1 cache configured to store a second plurality of entries;
the level N+1 cache configured to associate a first value with an entry upon receiving a request for the entry from the level N cache at which time the entry is to be copied from the level N+1 cache to the level N cache, the request configured to indicate Level N+1 cache entries currently stored in the level N cache, the first value configured to indicate that the entry is not to be aged in accordance with a Least Recently Used (LRU) policy implemented by the level N+1 cache, the level N+1 cache configured to maintain the first value until the entry is evicted from the level N cache, the level N+1 cache configured to associate the first value with entries within the level N+1 cache corresponding to the currently stored entries in the level N cache,
wherein after being notified that the entry has been evicted from the level N cache, the level N+1 cache is configured to associate a second value with the entry, the second value configured to indicate that the entry is to begin aging in accordance with the LRU policy implemented by the level N+1 cache.

2. The apparatus as in claim 1 wherein the level N cache comprises a CPU cache and wherein the level N+1 cache comprises a memory-side cache.

3. The apparatus as in claim 1 wherein the first value comprises a first LRU value to indicate which is to be maintained by the level N+1 cache until being notified that the entry has been evicted from the level N cache.

4. The apparatus as in claim 3 wherein the first value comprises a Super Most Recently Used value.

5. The apparatus as in claim 4 wherein the second value comprises a second LRU value to indicate the entry is the Most Recently Used of all other entries in the level N+1 cache except for any entries having Super Most Recently Used values.

6. The apparatus as in claim 5 wherein the level N cache is to apply its own LRU policy with respect to its own entries, thereby ageing and evicting entries in accordance with its own LRU policy.

7. An apparatus comprising:
a level N cache configured to store a first plurality of entries;
a level N+1 cache configured to store a second plurality of entries in a plurality of level N+1 cache Ways, the level N+1 cache configured to provide an entry to the level N cache upon receiving a request for the entry from the level N cache;
level N+1 cache synchronization logic configured to provide to the level N cache an indication of a level N+1 cache Way in the level N+1 cache in which the entry provided to the level N cache is stored, the level N cache configured to track the level N+1 cache Ways associated with each entry; and
level N cache synchronization logic configured to provide an indication to the level N+1 cache synchronization logic of the level N+1 cache Ways for which it currently has stored entries when making a request for one or more cache entries from the level N+1 cache, the level N+1 cache configured to perform evictions of entries based on the indication provided by the level N cache.

8. The apparatus as in claim 7 wherein the level N cache comprises a CPU cache and wherein the level N+1 cache comprises a memory-side cache.

9. The apparatus as in claim 7 wherein to perform evictions of entries based on the indication provided by the level N cache, the level N+1 cache is to implement a Least Recently Used (LRU) policy in which entries which are indicated to be the stored in the level N cache are assigned a value indicating that these entries are Super Most Recently Used (SMRU).

10. The apparatus as in claim 9 wherein the level N+1 cache is to refrain from modifying LRU values associated with the entries indicated to be in the level N cache until the level N cache synchronization logic provides an indication that one or more of these entries are no longer in the level N cache.

11. The apparatus as in claim 10 wherein upon receiving the indication that one or more of these entries are no longer in the level N cache, the level N+1 cache is to begin applying the LRU policy to these entries, thereby ageing and evicting entries in accordance with the LRU policy.

12. The apparatus as in claim 11 wherein the level N cache is to apply its own LRU policy with respect to its own entries, thereby ageing and evicting entries in accordance with its own LRU policy.

13. The apparatus as in claim 7 wherein the level N cache synchronization logic includes a first bus having a width equal to a number of Ways in each level N+1 cache Set, the level N cache synchronizing logic to use the first bus to communicate the indication of the level N+1 cache Ways for which it currently has stored entries in the form of a bit vector transmitted over the first bus.

14. The apparatus as in claim 13 wherein the level N+1 cache synchronization logic includes a second bus having a width of N where 2 N is greater than or equal to the number of Ways in the level N+1 cache, the level N+1 cache synchronization logic to use the second bus to communicate the indication of the level N+1 cache Way in the level N+1 cache in which the entry provided to the level N cache is stored.

15. The apparatus as in claim 13 wherein the level N+1 cache is organized into a plurality of Sets, each Set comprising the plurality of level N+1 cache Ways, wherein the number of level N+1 cache Sets is a multiple of the Sets of the level N cache, wherein the level N cache synchronization logic is aware of the multiple and only marks bits in the bit vector if they are relevant to the level N+1 cache Set responsible for handling each request.

16. The apparatus as in claim 7 wherein the level N cache includes a metadata component and a data component, both the metadata component and the data component stored on a common semiconductor die, and wherein the level N+1 cache also includes a metadata component and a data component, wherein at least a first portion of the metadata component of the level N+1 cache is stored on the common semiconductor die and wherein the data component is stored off of the common semiconductor die.

17. The apparatus as in claim 16 wherein a second portion of the metadata component of the level N+1 cache is stored off of the common semiconductor die.

18. A method comprising:
storing a first plurality of entries in a level N cache;
storing a second plurality of entries in a level N+1 cache within a plurality of level N+1 cache Ways;
providing an entry from the level N+1 cache to the level N cache upon receiving a request for the entry from the level N cache;
providing to the level N cache an indication of a level N+1 cache Way in the level N+1 cache in which the entry provided to the level N cache is stored, the level N cache to track the level N+1 cache Ways associated with each entry;
providing an indication to the level N+1 cache of the level N+1 cache Ways for which the level N cache currently has stored entries when making a request for one or more cache entries from the level N+1 cache; and
performing evictions of entries in the level N+1 cache at least partially based on the indication provided by the level N cache.

19. The method as in claim 18 wherein the level N cache comprises a Level 1 (L1) cache and wherein the level N+1 cache comprises a Level 2 (L2) cache.

20. The method as in claim 18 wherein performing evictions of entries based on the indication provided by the level N cache comprises:
implementin

Assignees

• Intel Corp

Inventors

• Greenspan Daniel
• Fanning Blaise
• Lossin Yoav
• Rubinstein Asaf

Classifications

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/123 Primary

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/60

  Details of cache memory · CPC title