Systems and methods for secure multi-access of system firmware during pre-boot

Patent metadata

Field	Value
Publication number	US-10055357-B2
Application number	US-201615058754-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Mar 2, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Systems and methods are provided that may be implemented to systems and methods that may be implemented to utilize direct memory access (DMA) remapping to control firmware updates and/or other configuration changes or device access control protocol for devices of an information handling system during the Unified Extensible Firmware Interface (UEFI) pre-boot phase before the booting the operating system (OS). The disclosed systems and methods may use DMA remapping during UEFI pre-boot to determine whether to allow or disallow pre-boot firmware updates and/or device configuration for hardware devices, and may be performed in the presence or absence of UEFI Secure Boot.

First claim

What is claimed is:

1. An information handling system, comprising:
at least one processing device configured to execute a host operating system (OS) for the information handling system; and
at least one given hardware device separate from the at least one processing device, the at least one given hardware device being coupled in data communication with the processing device;
where the processing device is configured to receive a requested firmware update for the given hardware device prior to loading the host operating system (OS) for the information handling system, the requested firmware update including a firmware-requested memory address for the given hardware device that is different from the actual hardware IO address for the given hardware device;
where the processing device is configured to respond to the requested firmware update by first determining prior to loading the host operating system (OS) whether the given hardware device has previously registered with DMA remapping information stored in memory of the information handling system for the given hardware device and whether the firmware-requested memory address matches the assigned DMA mapping address translation in the DMA remapping information for the given hardware device;
where the processing device is further configured to then either:
access and utilize the stored direct memory access (DMA) remapping information stored in memory of the information handling system to translate the firmware-requested memory address from the requested firmware update to the actual hardware IO device address for the given hardware device coupled to the processing device to perform a requested firmware update for the given hardware device prior to loading a host operating system (OS) for the information handling system when the processing device first determines prior to loading the host operating system (OS) that the given hardware device has previously registered with the DMA mapping for the given hardware device and determines prior to loading the host operating system (OS) that the firmware-requested memory address matches the assigned DMA mapping address translation for the given hardware device, or
prevent the requested firmware update for the given hardware device prior to loading the host operating system (OS) for the information handling system when the processing device determines that the given hardware device has not previously registered with the DMA mapping for the given hardware device or has determined that the firmware-requested memory address does not match the assigned DMA mapping address translation for the given hardware device.

2. The system of claim 1 , where the stored DMA remapping information includes a translation between the firmware-requested memory address and an actual hardware IO device address for the given hardware device, the DMA remapping information being stored within a system memory of the information handling system; and where the processing device is further configured to perform the following steps prior to loading the host OS:
receive an access request for the firmware update for the given hardware device and a firmware-requested memory address associated with the access request;
respond to the access request by accessing the stored DMA remapping information; and
use the DMA remapping information to translate the firmware-requested memory address to the actual hardware IO device address for the given hardware device to perform the requested firmware update for the given hardware device.

3. The system of claim 2 , where the processing device is further configured to perform the following steps prior to loading the host OS:
respond to the access request by accessing stored direct memory access (DMA) remapping information to determine if the given hardware device has been assigned a translation between a firmware-requested memory address and actual hardware IO device address for the given hardware device within the stored DMA remapping information; and then:
not access the system memory to perform the requested firmware update or other requested device access control protocol for the given hardware device if the given hardware device has not been assigned a translation between a firmware-requested memory address and actual hardware IO device address for the given hardware device; and
use the DMA remapping information to translate the firmware-requested memory address to the actual hardware IO device address to access the system memory to perform the requested firmware update for the given hardware device if the given hardware device has been assigned a translation between a firmware-requested memory address and actual hardware IO device address for the given hardware device.

4. The system of claim 1 , where the processing device is further configured to access and utilize stored direct memory access (DMA) remapping information to translate the firmware-requested memory address to an actual hardware IO device address for the given hardware device and to perform the requested firmware update for the given hardware device during a Driver Execution Environment (DXE) phase of Unified Extensible Firmware Interface (UEFI) pre-boot environment executing on the processing device.

5. The system of claim 1 , where the given hardware device comprises at least one of a basic input/output system (BIOS) flash memory device, non-volatile dual inline memory module (NVDIMM), volatile dual inline memory module (DIMM) device, power supply unit (PSU), complex programmable logic device (CPLD), or Peripheral Component Interconnect Express (PCIe) device.

6. The system of claim 1 , where the processing device is further configured to identify the presence of hardware devices coupled in data communication with the processing device and including the given hardware device during manufacture or assembly of the information handling system; and to then create DMA mapping for the identified hardware devices to control access to the identified hardware devices prior to loading the host OS.

7. The system of claim 6 , where the processing device is further configured to register each identified hardware device including coupled in data communication with the processing device and including the given hardware device; and to use the created DMA mapping to assign the DMA remapping information to translate a firmware-requested memory address to an actual hardware IO device address to control attempted accesses to the each identified hardware device.

8. The system of claim 1 , where the processing device is further configured to use the processing device during a UEFI non-Secure Boot pre-boot environment executing on the processing device to employ the DMA remapping information to generate a non-maskable interrupt (NMI) failure due to unauthorized access attempt to system memory to prevent an attempted access to a particular hardware device when the attempted access does not provide a correct DMA address translation for the particular hardware device.

9. The system of claim 1 , where the processing device is further configured to process the requested firmware update using firmware management protocol (FMP) executing on the at least one processing device.

10. The system of claim 1 , where the processing device is coupled in data communication with the given hardware device through a host bridge of the information handling system.

11. The system of claim 1 , where the processing device is further configured to perform all of the following steps prior to loading the host OS:
scan for the presence of particular platform IO devices including the given hardware device;
then use the results of the scan to create a map in the DMA mapping address transla

Assignees

• Vidyadhara Sumanth
• Nijhawan Vijay B
• Dell Products Lp

Inventors

• Vidyadhara Sumanth
• Nijhawan Vijay B

Classifications

• G06F21/57

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title