Interpreting signals received from redundant buses

Patent metadata

Field	Value
Publication number	US-10055322-B2
Application number	US-201315025565-A
Country	US
Kind code	B2
Filing date	Sep 30, 2013
Priority date	Sep 30, 2013
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A technique includes receiving a first signal from a first bus, and receiving a second signal from a second bus. The first and second buses are used for redundant communications. The technique includes interpreting the first and second signals to derive a bus data input signal for a controller based at least in part on detection of a predetermined bus fault.

First claim

What is claimed is:

1. A method comprising:
receiving a first signal from a first bus;
receiving a second signal from a second bus, the first and second buses being used for redundant communications;
deriving a bus data input signal as a logical ANDing of the first and second signals or as a logical ORing of the first and second signals, based on whether a predetermined bus fault has been detected; and
transmitting the bus data input signal to a controller.

2. The method of claim 1 , wherein:
in absence of the predetermined bus fault, the first and second buses are each adapted to communicate a recessive logic value and communicate a dominant logic value; and
the predetermined bus fault comprises a dominant bus fault such that when the dominant bus fault occurs with one of the first and second buses, the bus with which the fault occurs communicates dominant logic values independently of a signal being furnished to the bus by a transmitter.

3. The method of claim 1 , wherein deriving the bus data input signal comprises:
deriving the bus data input signal as the logical ORing of the first and second signals responsive to detection of the predetermined bus fault; and
deriving the bus data input signal as the logical ANDing of the first and second signals responsive to an absence of detection of the predetermined bus fault.

4. The method of claim 2 , further comprising:
determining whether communication over the first and second buses by a given bus device is impaired due to a recessive fault with one of the first and second buses, the recessive fault causing the bus with which the recessive fault occurs to communicate recessive logic values regardless of signals being furnished to the bus by the given bus device, wherein determining whether the communication by the given bus device is impaired due to the recessive bus fault comprises:
determining whether both the combined and fourth signals may be used to communicate with the given bus device.

5. The method of claim 1 , wherein the controller controls a device in accordance with the derived bus data input signal.

6. The method of claim 1 , wherein the derived bus data input signal is a correct base data signal regardless of whether the predetermined bus fault has occurred.

7. An apparatus comprising:
a fault detector to detect a predetermined fault occurring with a set of redundant buses, wherein the set of redundant buses comprises a first bus and a second bus, the first bus providing a first signal and the second bus providing a second signal;
a bus interface to logically AND the first and second signals to provide a third signal and logically OR the first and second signals to provide a fourth signal; and
a processor to communicate with the set of redundant buses, the processor to transmit one of the third and fourth signals as a bus data input signal to a controller based on whether the fault detector detects the predetermined fault.

8. The apparatus of claim 7 , wherein:
in absence of the predetermined bus fault, the first and second buses are each adapted to communicate a recessive logic value and communicate a dominant logic value; and
the predetermined bus fault comprises a dominant bus fault such that when the dominant bus fault occurs with one of the first and second buses, the bus with which the fault occurs communicates dominant logic values independently of a signal being furnished to the bus by a transmitter.

9. The apparatus of claim 8 , further comprising:
a recessive fault detector to detect a recessive fault, wherein the recessive fault occurs with one of the first and second buses when the bus with which the recessive fault occurs communicates recessive logic values independently of a signal being furnished to the bus by a transmitter.

10. An article comprising a non-transitory computer readable storage medium to store instructions that when executed by a computer cause the computer to:
detect a predetermined fault occurring with a set of redundant buses, wherein the set of redundant buses comprises a first bus and a second bus, the first bus providing a first signal and the second bus providing a second signal; and
derive a bus data input signal as a logical ANDing of the first and second signals or as a logical ORing of the first and second signals, based on whether the predetermined fault has been detected; and
transmit the bus data input signal to a controller.

11. The article of claim 10 , the storage medium storing instructions that when executed by the computer cause the computer to detect the predetermined fault by detecting an absence of communication over the first and second buses for a predetermined time interval.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Olson Alex Gunnar

Classifications

• G06F11/1625 Primary

  in communications, e.g. transmission, interfaces · CPC title

• G06F11/3027 Primary

  where the computing system component is a bus · CPC title

• G06F11/221

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title