Method of selectively removing an anti-stiction layer on a eutectic bonding area

US10053361B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10053361-B2
Application numberUS-201414583269-A
CountryUS
Kind codeB2
Filing dateDec 26, 2014
Priority dateDec 26, 2014
Publication dateAug 21, 2018
Grant dateAug 21, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A microelectromechanical systems (MEMS) package includes a eutectic bonding structure free of a native oxide layer and an anti-stiction layer, while also including a MEMS device having a top surface and sidewalls lined with the anti-stiction layer. The MEMS device is arranged within a MEMS substrate having a first eutectic bonding substructure arranged thereon. A cap substrate having a second eutectic bonding substructure arranged thereon is eutectically bonded to the MEMS substrate with a eutectic bond at the interface of the first and second eutectic bonding substructures. The anti-stiction layer lines a top surface and sidewalls of the MEMS device, but not the first and second eutectic bonding substructures. A method for manufacturing the MEMS package and a process system for selective plasma treatment are also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a microelectromechanical systems (MEMS) package, the method comprising: forming an anti-stiction layer lining uncovered surfaces of a MEMS device arranged within a MEMS substrate and lining a eutectic bonding substructure arranged on the MEMS substrate; forming a top electrode comprising a conductive layer, an electrode substrate under and contacting the conductive layer, and an electrode dielectric layer under and contacting the electrode substrate, wherein the conductive layer has outermost conductive layer sidewalls, the electrode substrate has outermost electrode substrate sidewalls, and the electrode dielectric layer has outermost electrode dielectric layer sidewalls, wherein the outermost conductive layer sidewalls, the outermost electrode substrate sidewalls, and the outermost electrode dielectric layer sidewalls are outermost and coplanar when viewed in cross-section, wherein forming the top electrode comprises forming the electrode dielectric layer with a pattern, and wherein forming the top electrode comprises forming the electrode dielectric layer as photoresist and the electrode substrate as glass; cleaning the eutectic bonding substructure by selectively removing regions of the anti-stiction layer lining the eutectic bonding substructure while leaving regions of the anti-stiction layer lining the MEMS device, wherein the cleaning comprises selectively forming plasma in a plasma chamber according to the pattern of the electrode dielectric layer using the top electrode and an underlying bottom electrode; and eutectically bonding a cap substrate over the MEMS device to the MEMS substrate using the cleaned eutectic bonding substructure. 2. The method according to claim 1 , further including: cleaning the eutectic bonding substructure by further selectively removing regions of a native oxide layer lining the eutectic bonding substructure while leaving regions of the native oxide layer lining the MEMS device. 3. The method according to claim 1 , further including: forming the MEMS device within a cavity arranged between the MEMS substrate and the cap substrate; and forming the eutectic bonding substructure around a periphery of the cavity. 4. The method according to claim 3 , further including: bonding an integrated circuit (IC) substrate below the MEMS substrate; and forming the cavity between the IC substrate, the MEMS substrate, and the cap substrate. 5. The method according to claim 1 , further including: forming MEMS bond pads over a top surface of the MEMS substrate, laterally spaced from the eutectic bonding substructure; and cleaning the MEMS bond pads by selectively removing regions of the anti-stiction layer lining the MEMS bond pads while leaving regions of the anti-stiction layer lining the MEMS device. 6. The method according to claim 1 , further including: bonding an integrated circuit (IC) substrate below the MEMS substrate; forming IC bond pads on the IC substrate; forming through silicon vias (TSVs) extending through the MEMS substrate, from a top surface of the MEMS substrate, and electrically coupling to corresponding ones of the IC bond pads; and forming MEMS bond pads corresponding to and electrically coupled to the TSVs over the top surface of the MEMS substrate. 7. The method according to claim 1 , further comprising: forming the anti-stiction layer covering a top surface of the MEMS device and a top surface of the eutectic bonding substructure, wherein the cleaning comprises removing the anti-stiction layer from the top surface of the eutectic bonding substructure without removing the anti-stiction layer from the top surface of the MEMS device. 8. The method according to claim 1 , further comprising: forming the top electrode with outer sidewalls between which the conductive layer, the electrode substrate, and the electrode dielectric layer are arranged, wherein the outer sidewalls of the top electrode are shared by the conductive layer, the electrode substrate, and the electrode dielectric layer; and positioning the top electrode within the plasma chamber with the outer sidewalls laterally spaced from sidewalls of the plasma chamber. 9. The method according to claim 1 , wherein forming the electrode dielectric layer with the pattern comprises forming a recess on a bottom of the electrode dielectric layer, wherein the recess is formed with opposite sidewalls extending continuously from a bottom surface of the electrode dielectric layer to a top surface of the electrode dielectric layer, and wherein the recess is formed with a top surface extending continuously from one of the opposite sidewalls to another one of the opposite sidewalls. 10. A method for manufacturing a microelectromechanical systems (MEMS) package, the method comprising: forming an anti-stiction layer covering a top surface of a MEMS device arranged in a substrate, and further covering a top surface of a conductive structure arranged over the substrate and spaced from the MEMS device; forming a top electrode comprising a conductive layer, an electrode substrate, and an electrode dielectric layer, wherein the electrode substrate is arranged between and contacting the conductive layer and the electrode dielectric layer, wherein the conductive layer has a pair of opposite conductive layer sidewalls, the electrode substrate has a pair of opposite electrode substrate sidewalls, and the electrode dielectric layer has a pair of opposite electrode dielectric layer sidewalls, wherein the opposite conductive layer sidewalls are respectively even with the opposite electrode substrate sidewalls, wherein the opposite electrode substrate sidewalls are respectively even with the opposite electrode dielectric layer sidewalls, wherein forming the top electrode comprises patterning the electrode dielectric layer to form a recess on a bottom of the top electrode, wherein the recess is formed with opposite sidewalls extending continuously from a bottom surface of the electrode dielectric layer to a bottom surface of the electrode substrate that is spaced between a top surface of the electrode substrate and the bottom surface of the electrode dielectric layer, wherein the bottom surface of the electrode substrate extends from one of the opposite sidewalls of the recess to another one of the opposite sidewalls of the recess, and wherein the bottom surface of the electrode substrate completely covers the recess when viewed in cross-section; and removing the anti-stiction layer from the top surface of the conductive structure, while leaving the anti-stiction layer covering the top surface of the MEMS device, using the top electrode and an underlying bottom electrode to selectively generate plasma in a plasma chamber. 11. The method according to claim 10 , wherein the conductive structure is a eutectic bond structure, and wherein the method further comprises: eutectically bonding a cap substrate to the eutectic bonding structure, such that the cap substrate covers the MEMS device. 12. The method according to claim 10 , wherein forming the top electrode comprises patterning the electrode dielectric layer to form the recess with a ring shape that extends laterally to enclose a central region of the top electrode, and wherein removing the anti-stiction layer comprises: positioning the substrate in the plasma chamber, between the top electrode and the underlying bottom electrode, such that the conductive structure directly underlies the recess and the MEMS device directly underlies the central region; and exposing the conductive structure to the plasma without exposing the MEMS device to the plasma, wherein the plasma is localized to di

Assignees

Inventors

Classifications

  • Bonding of solid lids or wafers to the substrate · CPC title

  • Bonding an individual cap on the substrate · CPC title

  • Apparatus specially adapted for the manufacture or treatment of microstructural devices or systems not provided for in B81C99/001 - B81C99/002 · CPC title

  • Anti-stiction coatings · CPC title

  • Cleaning during or after manufacture (cleaning of semiconductor devices H10P50/00) · CPC title

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What does patent US10053361B2 cover?
A microelectromechanical systems (MEMS) package includes a eutectic bonding structure free of a native oxide layer and an anti-stiction layer, while also including a MEMS device having a top surface and sidewalls lined with the anti-stiction layer. The MEMS device is arranged within a MEMS substrate having a first eutectic bonding substructure arranged thereon. A cap substrate having a second e…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification B81C99/0025. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Aug 21 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).