Oversampling digital receiver for radio-frequency signals

Patent metadata

Field	Value
Publication number	US-10051591-B2
Application number	US-201715601483-A
Country	US
Kind code	B2
Filing date	May 22, 2017
Priority date	Oct 4, 2005
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors produce processed representations of information contained in respective analog radio frequency representations.

First claim

What is claimed is:

1. A method for processing a radio frequency signal, comprising:
concurrently receiving a plurality of digitized modulated radio frequency signals representing a plurality of analog modulated radio frequency signals, each having a minimum sampling rate of at least 1 GHz, and an associated digital clock having a clock rate of at least 1 gigahertz;
receiving a switching control signal;
concurrently communicating a plurality of digitized modulated radio frequency signals, having a minimum sampling rate of 1 GHz, and a respective digital clock for each respective digitized modulated radio frequency signal with a non-blocking switch matrix to a plurality of correlator-based digital signal processors in dependence on the switching control signal; and
outputting information from the plurality of correlator-based digital signal processors, dependent on at least a modulation of the digitized modulated radio frequency signals, and a state of the switching control signal.

2. The method according to claim 1 , wherein the digital clock for at least two of the respective digitized radio frequency signals is independent.

3. The method according to claim 1 , wherein the plurality of digitized radio frequency signals each comprise a digitized modulated radio frequency carrier which is digitized at a clock rate above a respective Nyquist rate for the modulated radio frequency carrier.

4. The method according to claim 1 , wherein at least one respective digital clock has a clock rate in excess of 10 gigahertz.

5. The method according to claim 1 , wherein at least two digitized radio frequency signal are concurrently switched by the non-blocking switch matrix.

6. The method according to claim 1 , wherein at least one of the respective digitized radio frequency signals comprises a parallel multiple binary bit digital representation of an analog radio frequency signal.

7. The method according to claim 1 , further comprising matching a delay of a digitized radio frequency signal and respective digital clock to maintain synchronization therebetween.

8. The method according to claim 1 , further comprising selectively controlling a delay of a digitized radio frequency signal.

9. The method according to claim 1 , further comprising generating at least two digital clocks corresponding to at least two respective digitized modulated radio frequency signals, each having a different sampling rate in excess of 1 GHz radio frequencies.

10. The method according to claim 1 , further comprising altering the switching control signal to alter an output port of the non-blocking switch matrix for a digitized radio frequency signal and associated digital clock dynamically in real time.

11. The method according to claim 1 , further comprising processing at least one digitized radio frequency signal from the non-blocking switch matrix with a digital channelizing receiver.

12. The method according to claim 1 , further comprising cross correlating a digitized radio frequency signal from the non-blocking switch matrix at a clock rate of the respective digital clock.

13. The method according to claim 1 , wherein the non-blocking switch matrix comprises a Banyan network.

14. The method according to claim 1 , wherein the non-blocking switch matrix is configured to regenerate and simultaneously multicast the digitized plurality of radio frequency signals and the respective digital clock for each digitized radio frequency signal as at least two output data streams.

15. The method according to claim 1 , wherein the non-blocking switch matrix comprises a plurality of 2×2 superconducting switch networks, each switch network configured to receive a data signal and an associated data clock signal and to selectively direct a regenerated representation of the received data signal and the associated data clock signal to one of a first output and a second output, controlled in dependence on a set line and a reset line, the plurality of 2×2 superconducting switch networks being configured as an M×N cross-point switch matrix that connects M inputs to N outputs; and
a plurality of delay compensation networks configured to match delays of regenerated representations of the received data signals and the associated data clock signals at the N outputs.

16. The method according to claim 15 , wherein each superconducting switch network comprises at least four switch cells, each switch cell having a non-destructive readout (NDRO) switch, and being configured as a reset-set flip-flop (RSFF).

17. The method according to claim 15 , wherein each delay compensation network comprises a tunable Josephson transmission line.

18. A method for processing a radio frequency signal, comprising:
concurrently receiving a plurality of digitized modulated radio frequency signals representing a plurality of analog modulated radio frequency signals, each having a minimum sampling rate of at least 1 GHz, and an associated digital clock having a clock rate of at least 1 gigahertz;
receiving a switching control signal;
concurrently switching a plurality of digitized modulated radio frequency signals having a minimum sampling rate of 1 GHz, and a respective independent digital clock having a clock rate of at least 1 GHz accompanying each respective digitized radio frequency signal, with a Banyan network non-blocking switch matrix in dependence on the switching control signal to a respective plurality of correlators, in dependence on the switching control signal;
matching a delay of a respective digitized radio frequency signal and respective digital clock to maintain synchronization therebetween; and
outputting information from the plurality of correlator-based digital signal processors, dependent on at least a modulation of the digitized modulated radio frequency signals, and a state of the switching control signal.

19. The method according to claim 18 , further comprising altering the switching control signal, to thereby select dynamically in real time, a respective one of a plurality of output ports of the non-blocking switch matrix for a respective digitized radio frequency signal and associated digital clock.

20. A method for processing a radio frequency signal, comprising:
concurrently receiving a plurality of digitized modulated radio frequency signals representing a plurality of analog modulated radio frequency signals, each having a minimum sampling rate of at least 1 GHz, and an associated digital clock having a clock rate of at least 1 gigahertz;
receiving a switching control signal;
receiving a plurality of digitized modulated radio frequency signals and a plurality of independent digital clocks having a clock rate of at least 1 GHz accompanying each respective digitized radio frequency signal;
concurrently switching the plurality of digitized radio frequency signals and the plurality of independent digital clocks having a clock rate of at least 1 GHz accompanying each respective digitized radio frequency signal, with a non-blocking switch matrix configured to regenerate and simultaneously multicast the digitized plurality of radio frequency signals and the respective digital clock for each digitized modulated radio frequency signal as at least two output data streams, in dependence on the switching control signal, to a respective plurality of correlation-based signal processors;
matching a delay of a respective digitized radio frequency signal and respective digital clock to maintain synchronization therebetween; and
outputting a signal processing result from the respectiv

Assignees

• Hypres Inc

Inventors

• Gupta Deepnarayan

Classifications

• H04B1/005

  adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges · CPC title

• H04B1/0483

  Transmitters with multiple parallel paths · CPC title

• H04W56/0015 Primary

  one node acting as a reference for the others · CPC title

• H04B1/40

  Circuits · CPC title