CTLE gear shifting to enable CDR frequency lock in wired communication

Patent metadata

Field	Value
Publication number	US-10050814-B2
Application number	US-201715415918-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Jan 28, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

First claim

What is claimed is:

1. A receiver for operation under inter-signal interference (ISI), the receiver comprising:
a continuous time linear equalizer (CTLE) coupled to receive a pulse amplitude modulation (PAM) signal and to provide an equalized output signal;
a decision feedback equalizer (DFE) coupled to receive the equalized output signal and to provide recognized PAM data; and
a clock data recovery circuit (CDR) coupled to receive the equalized output signal and to provide a clock signal to the DFE;
wherein the CTLE is configured to: initiate operation using an initial equalization setting that is adapted for use without the DFE until clock acquisitions; and, responsive to a determination that a frequency lock has been achieved by the CDR, switch to a final equalization setting that is adapted for steady state operation with the DFE.

2. The receiver of claim 1 , further comprising a look-up table containing the initial equalization setting, one or more intermediate equalization settings and the final equalization setting.

3. The receiver of claim 1 , wherein the DFE comprises:
an adder having: an output; and a first input and a second input that are coupled to receive the equalized output signal and an output from a DFE feedback circuit respectively;
a data slicer having: an output; and an input coupled to the output of the adder;
a data buffer having: an input coupled to the output of the data slicer; and an output to provide the recognized PAM data.

4. The receiver of claim 1 , wherein the CTLE is configured to switch to the final equalization setting responsive to a determination that the DFE has settled to a steady state.

5. The receiver of in claim 1 , wherein the CTLE is configured to switch to the final equalization setting responsive to a determination that an infinite impulse response (IIR) is operational in the DFE.

6. The receiver of claim 2 , wherein the CTLE is configured to switch to one of the intermediate settings responsive to a determination that the DFE has settled to a steady state.

7. The receiver of claim 2 , wherein the CTLE is configured to switch to one of the intermediate settings responsive to a determination that the CDR has achieved frequency or phase lock.

8. The receiver of claim 2 , wherein the CTLE is configured to switch to one of the intermediate settings responsive to switching the CDR from a Pottbäcker phase frequency detector (PFD) to a pulse amplitude modulation phase detector (PAMPD).

9. The receiver of claim 1 , wherein the initial equalization setting is set to provide strong equalization by the CTLE to facilitate phase and frequency locking of the CDR in an absence of DFE equalization.

Assignees

• Texas Instruments Inc

Inventors

• Hoshyar Reza
• Zheng Kevin
• Warke Nirmal
• Zhou Wenting
• Kiaei Ali
• Bahai Ahmad

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03636

  Algorithms using least mean square [LMS] · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title