Low complexity sequence estimator for general packet radio service (GPRS) system

Patent metadata

Field	Value
Publication number	US-10050813-B2
Application number	US-201615390132-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Oct 25, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method and apparatus are provided. The method includes receiving, by a user equipment (UE), a phase shift keying (PSK) modulated signal from a transceiver, derotating the PSK modulated signal, and equalizing the PSK modulated signal using a maximum likelihood sequence estimator (MLSE) based on a first main tap gain (MTG) look up table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples and a second MTG LUT and a second ISI LUT corresponding to odd time samples.

First claim

What is claimed is:

1. A method, comprising:
receiving, by a user equipment (UE), a phase shift keying (PSK) modulated signal from a transceiver;
derotating the PSK modulated signal;
equalizing the PSK modulated signal using a maximum likelihood sequence estimator (MLSE) based on a first main tap gain (MTG) look up table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples and a second MTG LUT and a second ISI LUT corresponding to odd time samples;
multiplexing the even and odd MTG time samples; and
multiplexing the even and odd ISI time samples,
wherein the MLSE receives the multiplexed even and odd ISI time samples through an ISI multiplexor and the multiplexed even and odd MTG time samples through an MTG multiplexor in order to generate a soft value.

2. The method of claim 1 , further comprising:
reducing one of a branch sequence estimation and a state sequence estimation in the MLSE; and
determining a soft symbol based on the one of the reduced branch sequence estimation and the reduced state sequence estimation in the MLSE,
wherein the MLSE reduces the state sequence estimation by partitioning candidate symbols according to a Euclidian distance between the symbols.

3. The method of claim 1 , wherein the MLSE uses a log-likelihood ratio saturation process.

4. The method of claim 1 , wherein the MLSE derotates the PSK modulated signal by an integer multiple of π/4.

5. The method of claim 1 , wherein the PSK modulated signal is received by a UE that includes single antenna interference cancelation processing.

6. The method of claim 2 , wherein the branch sequence estimation is reduced to two branches.

7. The method of claim 1 , wherein the first MTG LUT, the first ISI LUT, the second MTG LUT, and the second ISI LUT are updated with new values when channel estimation is performed and channel state information is updated.

8. The method of claim 1 , wherein the MLSE executes a soft Viterbi algorithm.

9. The method of claim 8 , wherein the soft Viterbi algorithm receives the multiplexed even and odd ISI time samples through the ISI multiplexor and the multiplexed even and odd MTG time samples through the MTG multiplexor.

10. The method of claim 1 , wherein the UE transmits and receives signals corresponding to at least one of global system for mobile communication (GSM), general packet radio service (GPRS), enhanced data rates for GSM evolution (EDGE), long term evolution (LTE), fifth generation (5G), long term evolution advanced (LTE-A), code division multiple access (CDMA), wideband code division multiple access (WCDMA), and universal mobile telecommunications system (UMTS).

11. An apparatus, comprising:
a processor; and
a receiver configured to:
receive a phase shift keying (PSK) modulated signal from a transceiver,
derotate the PSK modulated signal,
input the PSK modulated signal to a maximum likelihood sequence estimator (MLSE), wherein the MLSE includes a first main tap gain (MTG) look up table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples, and a second MTG LUT and a second ISI LUT corresponding to odd time samples,

multiplex the even and odd MTG time samples, and
multiplex the even and odd ISI time samples,
wherein the MLSE receives the multiplexed even and odd ISI time samples through an ISI multiplexor and the multiplexed even and odd MTG time samples through an MTG multiplexor in order to generate a soft value.

12. The apparatus of claim 11 , wherein the receiver is further configured to:
reduce a branch sequence estimation in the MLSE, or
reduce a state sequence estimation in the MLSE, and
determine a soft symbol based on the branch sequence estimation or the state sequence estimation in the MLSE, wherein the MLSE reduces the state sequence estimation by partitioning candidate symbols according to a Euclidian distance between the symbols.

13. The apparatus of claim 11 , wherein the MLSE uses a log-likelihood ratio saturation process.

14. The apparatus of claim 11 , wherein the MLSE derotates the PSK modulated signal by an integer multiple of π/4.

15. The apparatus of claim 11 , the receiver includes single antenna interference cancelation processing.

16. The apparatus of claim 12 , wherein the branch sequence estimation is reduced to two branches.

17. The apparatus of claim 11 , wherein the first MTG LUT, the first ISI LUT, the second MTG LUT, and the second ISI LUT are updated with new values when channel estimation is performed and channel state information is updated.

18. The apparatus of claim 11 , wherein the MLSE executes a soft Viterbi algorithm.

19. The apparatus of claim 18 , wherein the soft Viterbi algorithm receives the multiplexed even and odd ISI time samples through the ISI multiplexor and the multiplexed even and odd MTG time samples through the MTG multiplexor.

20. A method of manufacturing a processor, comprising:
forming the processor as part of a wafer or package that includes at least one other processor, wherein the processor is configured to receive, by a user equipment (UE), a phase shift keying (PSK) modulated signal from a transceiver, derotate the PSK modulated signal, and input the PSK modulated signal to a phase-rotated maximum likelihood sequence estimator (MLSE),
wherein the MLSE includes a first main tap gain (MTG) look up table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples and a second MTG LUT and a second ISI LUT corresponding to odd time samples,
wherein the MLSE is configured to multiplex the even and odd MTG time samples, and multiplex the even and odd ISI time samples, and
wherein the MLSE receives the multiplexed even and odd ISI time samples through an ISI multiplexor and the multiplexed even and odd MTG time samples through an MTG multiplexor in order to generate a soft value.

21. A method of constructing an integrated circuit, comprising:
generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features that include a processor configured to receive, by a user equipment (UE), a phase shift keying (PSK) modulated signal from a transceiver, derotate the PSK modulated signal, and input the PSK modulated signal to a phase-rotated maximum likelihood sequence estimator (MLSE),
wherein the MLSE includes a first main tap gain (MTG) look up table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples and a second MTG LUT and a second ISI LUT corresponding to odd time samples,
wherein the MLSE is configured to multiplex the even and odd MTG time samples, and multiplex the even and odd ISI time samples, and
wherein the MLSE receives the multiplexed even and odd ISI time samples through an ISI multiplexor and the multiplexed even and odd MTG time samples through an MTG multiplexor in order to generate a soft value.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Song Kee-Bong
• Pandana Charles

Classifications

• H04L27/22

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/71057

  using maximum-likelihood sequence estimation [MLSE] · CPC title

• H04L1/0054

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

• H04L25/03006 Primary

  Arrangements for removing intersymbol interference · CPC title

• H04L25/03318

  Provision of soft decisions · CPC title