Interleaved dual output charge pump

Patent metadata

Field	Value
Publication number	US-10050522-B2
Application number	US-201514861058-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Feb 15, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

According to some implementation, a charge pump includes a boost charge pump circuit and a buck charge pump circuit sharing a common flying capacitance. In some implementations, the boost pump circuit includes an input node and a boosted-voltage output node, and the buck charge pump circuit includes the input node and a divided-voltage output node. In some implementations, the charge pump of claim 3 wherein the boosted-voltage includes 2×Vin, and the divided-voltage includes Vin/2, Vin being an input voltage at the input node. In some implementations, the boost pump circuit further includes a first holding capacitance that couples the boosted-voltage output node to a ground. In some implementations, the buck pump circuit further includes a second holding capacitance that couples the divided-voltage output node to the ground.

First claim

What is claimed is:

1. A charge pump comprising a boost charge pump circuit including an input node and a boosted-voltage output node, and a buck charge pump circuit including the input node and a divided-voltage output node sharing a common flying capacitance, the common flying capacitance configured to be partially charged to less than an input voltage during a phase of output voltage generation and configured to undergo truncated charging to limit a ripple effect in a hysteretic feedback loop, the boost charge pump circuit including a first holding capacitance that couples the boosted-voltage output node to a ground, the boost charge pump circuit and the buck charge pump circuit each including a plurality of switches implemented to incorporate the common flying capacitance and generate output voltages having magnitudes 2×Vbatt and Vbatt/2 respectively.

2. The charge pump of claim 1 wherein said plurality of switches includes a first switch (S 1 ) and a second switch (S 2 ) arranged in parallel between the input node and respective ends of the flying capacitance.

3. The charge pump of claim 2 wherein said plurality of switches includes a third switch (S 3 ) between the second end of the flying capacitance and the ground.

4. The charge pump of claim 3 wherein said plurality of switches includes a fourth switch (S 4 ) between the first end of the flying capacitance and the boosted-voltage output node.

5. The charge pump of claim 4 wherein said plurality of switches includes a fifth switch (S 5 ) between the first end of the flying capacitance and the divided-voltage output node.

6. The charge pump of claim 1 wherein the buck pump circuit further includes a second holding capacitance that couples the divided-voltage output node to the ground.

7. The charge pump of claim 5 wherein said plurality of switches includes a sixth switch (S 6 ) between the second end of the flying capacitance and the divided-voltage output node.

8. The charge pump of claim 7 wherein the switches S 1 , S 2 , S 3 , S 4 , S 5 and S 6 are configured to operate in four phases to yield the output voltages having magnitudes 2×Vbatt and Vbatt/2.

9. The charge pump of claim 8 wherein the first phase includes closed S 1 and S 6 and open S 2 to S 5 , the second phase includes closed S 3 and S 5 and open S 1 , S 2 , S 4 and S 6 , the third phase includes closed S 1 and S 3 and open S 2 and S 4 to S 6 , and the fourth phase includes closed S 2 and S 4 and open S 1 , S 3 , S 5 and S 6 .

10. The charge pump of claim 8 wherein the first phase includes closed S 1 and S 6 and open S 2 to S 5 , the second phase includes closed S 3 and S 5 and open S 1 , S 2 , S 4 and S 6 , the third phase includes closed S 1 and S 6 and open S 2 to S 5 , and the fourth phase includes closed S 2 and S 4 and open S 1 , S 3 , S 5 and S 6 .

11. The charge pump of claim 10 wherein the third phase includes partial charging of the flying capacitance to improve charge preservation.

12. The charge pump of claim 8 wherein the first phase includes closed S 1 and S 6 and open S 2 to S 5 , the second phase includes closed S 3 and S 5 and open S 1 , S 2 , S 4 and S 6 , the third phase includes closed S 1 and S 6 and open S 2 to S 5 , and the fourth phase includes closed S 3 and S 5 and open S 1 , S 2 , S 4 and S 6 .

13. The charge pump of claim 12 wherein the fourth phase includes truncated charging of the flying capacitance to limit ripple effect in hysteretic feedback loop.

14. A voltage supply system comprising:
a boost converter configured to generate a boosted voltage based on a battery voltage Vbatt; and
a charge pump having a boost charge pump circuit including an input node and a boosted-voltage output node, and a buck charge pump circuit including the input node and a divided-voltage output node sharing a common flying capacitance, the common flying capacitance configured to be partially charged to less than an input voltage during a phase of output voltage generation and configured to undergo truncated charging to limit ripple effect in a hysteretic feedback loop, the boost charge pump circuit including a first holding capacitance that couples the boosted-voltage output node to a ground, the boost charge pump circuit and the buck charge pump circuit each including a plurality of switches implemented to incorporate the common flying capacitance and generate output voltages having magnitudes 2×Vbatt and Vbatt/2 respectively.

15. The voltage supply system of claim 14 wherein the buck pump circuit further includes a second holding capacitance that couples the divided-voltage output node to the ground.

16. The voltage supply system of claim 15 wherein said plurality of switches includes a first switch (S 1 ) and a second switch (S 2 ) arranged in parallel between the input node and respective ends of the flying capacitance, a third switch (S 3 ) between the second end of the flying capacitance and the ground, a fourth switch (S 4 ) between the first end of the flying capacitance and the boosted-voltage output node, a fifth switch (S 5 ) between the first end of the flying capacitance and the divided-voltage output node, and a sixth switch (S 6 ) second end of the flying capacitance and the divided-voltage output node.

17. The voltage supply system of claim 16 wherein switches S 1 , S 2 , S 3 , S 4 , S 5 and S 6 are configured to operate in four phases to yield the output voltages having magnitudes 2×Vbatt and Vbatt/2.

18. A radio-frequency (RF) module comprising:
a packaging substrate configured to receive a plurality of components; and
a power amplification system implemented on the packaging substrate, the power amplification system including a voltage supply system, the voltage supply system including a charge pump having a boost charge pump circuit including an input node and a boosted-voltage output node, and a buck charge pump circuit including the input node and a divided-voltage output node sharing a common flying capacitance, the common flying capacitance configured to be partially charged to less than an input voltage during a phase of output voltage generation and configured to undergo truncated charging to limit ripple effect in a hysteretic feedback loop, the boost charge pump circuit including a first holding capacitance that couples the boosted-voltage output node to a ground, the boost charge pump circuit and the buck charge pump circuit each including a plurality of switches implemented to incorporate the common flying capacitance and generate output voltages having magnitudes 2×Vbatt and Vbatt/2 respectively.

19. The RF module of claim 18 wherein;
the buck pump circuit further includes a second holding capacitance that couples the divided-voltage output node to the ground.

20. The RF module of claim 19 wherein said plurality of switches includes a first switch (S 1 ) and a second switch (S 2 ) arranged in parallel between the input node and respective ends of the flying capacitance, a third switch (S 3 ) between the second end of the flying capacitance and the ground, a fourth switch (S 4 ) between the first end of the flying capacitance and the boosted-voltage output node, a fifth switch (S 5 ) between the first end of the flying capacitance and the divided-voltage output node, and a sixth switch (S 6 ) between the second end of the flying capacitance and the divided-voltage output node.

Assignees

• Skyworks Solutions Inc

Inventors

• Scheel Michael Lee

Classifications

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M2003/072

  Electricity · mapped topic

• H02M2001/009

  Electricity · mapped topic

• H02M2003/076

  Electricity · mapped topic

• H02M3/076

  the clock signals being boosted to a value being higher than the input voltage value · CPC title