Monolithic WDM VCSEL arrays by quantum well intermixing

Patent metadata

Field	Value
Publication number	US-10050414-B2
Application number	US-201515543233-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

An array of monolithic wavelength division multiplexed (WDM) vertical cavity surface emitting lasers (VCSELs) is provided with quantum well intermixing. Each VCSEL includes a bottom distributed Bragg reflector (DBR), an upper distributed Bragg reflector, and a laser cavity therebetween. The laser cavity includes a multiple quantum well (MQW) layer sandwiched between a lower separate confinement heterostructure (SCH) and an upper SCH layer. Each MQW region experiences a different amount of quantum well intermixing and concomitantly a different lasing wavelength shift.

First claim

What is claimed is:

1. An array of monolithic wavelength division multiplexed (WDM) vertical cavity surface emitting lasers (VCSELs) with quantum well intermixing, each VCSEL including a bottom distributed Bragg reflector (DBR), an upper distributed Bragg reflector, and a laser cavity therebetween, wherein the laser cavity includes a multiple quantum well (MQW) layer sandwiched between a lower separate confinement heterostructure (SCH) layer and an upper SCH layer, each MQW layer experiencing a different amount of quantum well intermixing and concomitantly a different lasing wavelength shift.

2. The array of claim 1 , in which the lower and upper DBRs comprise layers of GaAs and AlGaAs, the lower and upper SCH layers comprise AlGaAs, and the MQW comprises layers of InGaAs or GaAs, and AlGaAs or InGaP or GaAsP.

3. The array of claim 1 , in which the VCSELs are arranged in a linear fashion, each VCSEL having more quantum well intermixing in a particular direction, each VCSEL emitting light of a wavelength that is blue-shifted in the direction of more quantum well intermixing.

4. The array of claim 3 , in which the concentration of point defects arises from stress mismatch, with a greater number of point defects resulting in a larger quantum well intermixing.

5. An array of monolithic wavelength division multiplexed (WDM) vertical cavity surface emitting lasers (VCSELs) with quantum well intermixing, each VCSEL including a bottom distributed Bragg reflector (DBR), a upper distributed Bragg reflector, and a laser cavity therebetween, wherein the laser cavity may include a multiple quantum well (MQW) layer sandwiched between a lower separate confinement heterostructure (SCH) layer, and an upper SCH layer, each MQW experiencing a different amount of quantum well intermixing and concomitantly a different wavelength shift,
wherein each VCSEL further includes a Fabry Perot cavity tuning layer as part of the laser cavity, the Fabry Perot cavity tuning layer having a length that varies from one VCSEL to another.

6. The array of claim 5 , in which the lower and upper DBRs comprise layers of GaAs and AlGaAs, the lower and upper SCH layers comprise AlGaAs, and the MQW comprises layers of GaAs or InGaAs, and AlGaAs or InGaP or GaAsP.

7. The array of claim 5 , in which the VCSELs are arranged in a linear fashion, each VCSEL having a larger quantum well intermixing in a particular direction, each VCSEL emitting light of a wavelength that is blue-shifted in the direction of larger quantum well intermixing.

8. The array of claim 7 , in which the concentration of point defects arises from stress mismatch, with a greater number of point defects resulting in a larger quantum well intermixing.

9. The array of claim 5 , in which the Fabry Perot cavity tuning layer comprises part or all of the upper SCH layer.

10. A method of manufacturing an array of monolithic wavelength division multiplexed (WDM) vertical cavity surface emitting lasers (VCSELs) with quantum well intermixing, each VCSEL including a multiple quantum well and emitting light at a different wavelength from the others, each quantum well comprising a plurality of alternating quantum well and barrier layers, the method including:
providing a plurality of the multiple quantum wells; and
adding point defects to each multiple quantum well to intermix the quantum well and barrier layers,

wherein different concentrations of point defects induce different amounts of intermixing in the multiple quantum well and different wavelengths of light.

11. The method of claim 10 , wherein the point defects are created by:
forming a stress-inducing layer on top of a portion of a sacrificial layer to create point defects in a portion of the sacrificial layer; and
subjecting the portion to an elevated temperature for a period of time to drive the point defects toward the multiple quantum well layer.

12. The method of claim 10 , comprising:
providing a substrate;
forming on the substrate, in turn, a lower distributed Bragg reflector and a cavity comprising lower separate confinement heterostructure (SCH) layer, the multiple quantum well layer, and an upper SCH layer;
forming a sacrificial layer on top of the upper SCH layer;
forming a stress-inducing layer on top of a portion or the sacrificial layer to create point defects in a portion of the sacrificial layer;
subjecting the portion to a first elevated temperature for a period of time to drive the point defects toward the multiple quantum well layer to induce quantum well intermixing;
removing the stress-inducing layer;
repeating the steps of forming the stress-inducing layer on another portion of the sacrificial layer, subjecting the portion to a second elevated temperature, which may or may not be the same as the first elevated temperature, and removing the stress-inducing layer and the sacrificial layer;
forming on the upper SCH layer an upper distributed Bragg reflector; and
forming individual VCSELs by removing unwanted layers comprising the upper distributed Bragg reflector and the cavity, and forming an oxide aperture an ohmic contacts.

13. The method of claim 12 , in which the point defects are driven toward the multiple quantum well layer by rapid thermal annealing.

14. The method of claim 10 , in which a Fabry Perot cavity tuning layer is formed with the upper SCH layer, and comprises part or all of the upper SCH layer, wherein the Fabry Perot cavity tuning layer has length that varies from one VCSEL to another.

15. The method of claim 14 , comprising:
providing a substrate;
forming on the substrate, in turn, a lower distributed Bragg reflector and a cavity comprising lower SCH layer, the multiple quantum well layer, and an upper SCH layer with the Fabry Perot cavity tuning layer;
forming a sacrificial layer on top of the upper SCH layer;
forming a stress-inducing layer on top of a portion of the sacrificial layer to create point defects in a portion of the sacrificial layer;
subjecting the portion to a first elevated temperature for a period of time to drive the point defects toward the multiple quantum well layer to induce quantum well intermixing;
removing the tress-inducing layer;
repeating the steps of forming the stress-inducing layer on another portion of the sacrificial layer, subjecting the portion to a second elevated temperature, which may or may not be the same as the first elevated temperature, thinning a portion of the Fabry Perot cavity and removing the stress-inducing layer and the sacrificial layer;
forming on the upper SCH layer an upper distributed Bragg reflector; and
forming individual VCSELs by removing unwanted layers comprising the upper distributed Bragg reflector and the cavity, and forming an oxide aperture and ohmic contacts.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Mathai Sagi Varghese
• Tan Michael Renne Ty

Classifications

• H01S5/426

  Vertically stacked cavities · CPC title

• H01S5/423

  having a vertical cavity · CPC title

• H01S5/34326

  with a well layer based on InGa(Al)P, e.g. red laser · CPC title

• H01S5/18358 Primary

  containing spacer layers to adjust the phase of the light wave in the cavity · CPC title

• H01S5/026

  Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) · CPC title