Transistor, semiconductor device, and electronic device

Patent metadata

Field	Value
Publication number	US-10050152-B2
Application number	US-201615378143-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Dec 16, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. An electrode is provided over an oxide semiconductor layer A, the oxide semiconductor layer A and the electrode are covered with a layer C, and then heat treatment is performed; thus, oxidation of the electrode which is caused in the heat treatment is prevented. For the layer C, for example, an oxide semiconductor can be used. By covering a side surface of the oxide semiconductor layer A where a channel is formed with the layer C and the oxide semiconductor layer B, diffusion of impurities from the side surface of the oxide semiconductor layer A into the oxide semiconductor layer A is prevented.

First claim

What is claimed is:

1. A transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer;
a third oxide semiconductor layer;
a first electrode;
a second electrode;
a third electrode;
a first insulating layer; and
a first layer,
wherein the first oxide semiconductor layer has an island-like shape,
wherein the second oxide semiconductor layer has an island-like shape,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer overlap with each other in a region,
wherein the second oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the third region is located between the first region and the second region,
wherein the first electrode is located over the first region,
wherein the second electrode is located over the second region,
wherein the first layer does not cover a side surface of the first electrode on the third region side,
wherein the first layer does not cover a side surface of the second electrode on the third region side,
wherein the first layer comprises:
a region in contact with an upper surface of the first electrode;
a region in contact with a side surface of the first electrode on a side opposite to the third region side;
a region in contact with an upper surface of the second electrode; and
a region in contact with a side surface of the second electrode on a side opposite to the third region side,

wherein the third oxide semiconductor layer comprises:
a region overlapping with the first layer; and
a region in contact with the third region,

wherein the third oxide semiconductor layer covers a side surface of the second oxide semiconductor layer with the first layer located between the third oxide semiconductor layer and the side surface of the second oxide semiconductor layer,
wherein the first insulating layer is located over the third oxide semiconductor layer,
wherein the third electrode is located over the first insulating layer, and
wherein the third electrode comprises a region overlapping with the third region with the first insulating layer located between the region and the third region.

2. The transistor according to claim 1 , wherein the first layer comprises a region in contact with the side surface of the second oxide semiconductor layer.

3. The transistor according to claim 1 , wherein the first layer comprises a region in contact with a side surface of the first oxide semiconductor layer.

4. The transistor according to claim 1 , further comprising:
a second insulating layer; and
a fourth electrode,
wherein the second insulating layer is located under the first oxide semiconductor layer,
wherein the fourth electrode is located under the second insulating layer, and
wherein the fourth electrode comprises a region overlapping with the third region with the second insulating layer located between the region and the third region.

5. The transistor according to claim 1 , wherein a channel is formed in the third region.

6. The transistor according to claim 1 , wherein the second oxide semiconductor layer comprises at least one of In and Zn.

7. The transistor according to claim 1 , wherein the first oxide semiconductor layer and the third oxide semiconductor layer contain a metal element that is the same kind as at least one metal element contained in the second oxide semiconductor layer.

8. The transistor according to claim 1 , wherein the first layer contains a metal element that is the same kind as at least one metal element contained in the second oxide semiconductor layer.

9. The transistor according to claim 1 , wherein the first layer comprises an oxide semiconductor.

10. A semiconductor device comprising:
the transistor according to claim 1 ; and
a capacitor or a resistor.

11. An electronic device comprising:
the transistor according to claim 1 ; and
an antenna, a battery, an operation switch, a microphone, or a speaker.

12. A transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer;
a third oxide semiconductor layer;
a first electrode; and
a first layer,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer overlap with each other,
wherein the second oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the third region is located between the first region and the second region,
wherein the first electrode is located over the first region,
wherein the first layer does not cover a side surface of the first electrode on the third region side,
wherein the first layer comprises:
a region in contact with an upper surface of the first electrode; and
a region in contact with a side surface of the first electrode on a side opposite to the third region side,

wherein the third oxide semiconductor layer comprises:
a region overlapping with the first layer; and
a region in contact with the third region, and

wherein the third oxide semiconductor layer covers a side surface of the second oxide semiconductor layer with the first layer located between the third oxide semiconductor layer and the side surface of the second oxide semiconductor layer.

13. The transistor according to claim 12 , wherein the first layer comprises a region in contact with the side surface of the second oxide semiconductor layer.

14. The transistor according to claim 12 , wherein the first layer comprises a region in contact with a side surface of the first oxide semiconductor layer.

15. The transistor according to claim 12 , wherein the second oxide semiconductor layer comprises at least one of In and Zn.

16. The transistor according to claim 12 , wherein the first oxide semiconductor layer and the third oxide semiconductor layer contain a metal element that is the same kind as at least one metal element contained in the second oxide semiconductor layer.

17. The transistor according to claim 12 , wherein the first layer contains a metal element that is the same kind as at least one metal element contained in the second oxide semiconductor layer.

18. The transistor according to claim 12 , wherein the first layer comprises an oxide semiconductor.

19. A semiconductor device comprising:
the transistor according to claim 12 ; and
a capacitor or a resistor.

20. An electronic device comprising:
the transistor according to claim 12 ; and
an antenna, a battery, an operation switch, a microphone, or a speaker.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L27/1225

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic