Method of forming a polysilicon sidewall oxide region in a memory cell

Patent metadata

Field	Value
Publication number	US-10050131-B2
Application number	US-201615375094-A
Country	US
Kind code	B2
Filing date	Dec 11, 2016
Priority date	Dec 10, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

First claim

The invention claimed is:

1. A method of fabricating a memory cell of a semiconductor device, the method comprising:
depositing a conductive layer having a top surface and a side surface;
forming a partial ONO layer over the top surface of the conductive layer by depositing a first oxide layer on the top surface of the conductive layer and a silicon nitride layer on top of the first oxide layer, wherein the side surface of the conductive layer remains exposed; and
forming a sidewall oxide layer adjacent the side surface of the conductive layer by a process including:
depositing a high temperature oxide (HTO) film directly on the side surface of the conductive layer and on top of the silicon nitride layer thereby forming the ONO layer; and
performing a rapid thermal oxidation (RTO) anneal.

2. The method of claim 1 , wherein the sidewall oxide layer is formed by depositing the HTO film on the side surface of the conductive layer and subsequently performing the RTO anneal of the deposited HTO film.

3. The method of claim 1 , wherein the deposited HTO film has a thickness in a range of 50-120 Å.

4. The method of claim 1 , wherein the deposited HTO film has a thickness in a range of 60-80 Å.

5. The method of claim 1 , wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1000° C.-1200° C. for a duration in the range of 25-60 sec.

6. The method of claim 1 , wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1050° C.-1150° C. for a duration in a range of 30-40 sec.

7. The method of claim 1 , wherein the sidewall oxide layer is formed by performing the RTO anneal of the conductive layer and the partial ONO layer, and after the RTO anneal, depositing the HTO film over the side surface of the conductive layer.

8. The method of claim 7 , wherein:
the RTO anneal oxidizes the exposed side surface of the conductive layer, and
the HTO film is deposited on the oxidized side surface of the conductive layer.

9. A method of fabricating a memory cell of a semiconductor device, the method comprising:
forming a stack structure on a wafer by:
depositing a conductive layer on a first oxide layer;
forming a second oxide layer over a top surface of the conductive layer,
forming a silicon nitride layer over the top surface of the first oxide layer, and
forming and patterning a protective photoresist layer silicon nitride layer and performing an etching down to the first oxide layer, wherein a side surface of the conductive layer remains exposed;

depositing a high temperature oxide (HTO) film immediately on the side surface of the conductive layer and on top of the silicon nitride layer; and
performing a rapid thermal oxidation (RTO) anneal.

10. The method of claim 9 , wherein a sidewall oxide layer is formed by depositing the HTO film on the side surface of the conductive layer and subsequently performing the RTO anneal of the deposited HTO film.

11. The method of claim 9 , wherein the deposited HTO film has a thickness in a range of 50-120 Å.

12. The method of claim 9 , wherein the deposited HTO film has a thickness in a range of 60-80 Å.

13. The method of claim 9 , wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1000° C.-1200° C. for a duration in the range of 25-60 sec.

14. The method of claim 9 , wherein the RTO anneal is performed in a dry O2 environment, in a temperature range of 1050° C.-1150° C. for a duration in a range of 30-40 sec.

15. The method of claim 9 , wherein the second oxide layer has a thickness between 60-120 Å and the silicon nitride layer has a thickness between 60-200 Å.

16. The method of claim 9 , wherein a sidewall oxide layer is formed by performing the RTO anneal of the stack structure, and after the RTO anneal, depositing the HTO film over the side surface of the conductive layer.

17. The method of claim 16 , wherein:
the RTO anneal oxidizes the side surface of the conductive layer, and
the HTO film is deposited on the oxidized side surface of the conductive layer.

18. The method of claim 9 , further comprising the step of cleaning the wafer after forming the stack structure.

19. The method of claim 9 , wherein a total thickness of an oxide layer following the RTO anneal is between 50 and 120 Å on top of the silicon nitride layer, between 100 and 500 Å on the side surface of the conductive layer, and between 100 and 300 Å above a substrate.

Assignees

• Microchip Tech Inc

Inventors

• Wong Jack
• Kabeer Sajid
• Hymas Mel
• Murali Santosh
• Kopp Brad

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6529

  by exposure to a gas or vapour · CPC title

• H10P14/6519

  the substance being oxygen · CPC title

• H10P14/6516

  of treatments performed after formation of the materials · CPC title