Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10050087-B1
Application number	US-201715699500-A
Country	US
Kind code	B1
Filing date	Sep 8, 2017
Priority date	Mar 16, 2017
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate comprising a surface extending in a first direction and a second direction intersecting the first direction; and
a memory cell array disposed above the substrate, the memory cell array comprising: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; a select transistor including a channel layer and provided between the second wiring line and the third wiring line; and an insulating layer disposed between an end of the second wiring line in the third direction and the third wiring line,
wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select transistor comprises the first material
the memory cell further comprises a second layer,
the select transistor further comprises a gate insulating layer,
the second layer of the memory cell comprises a second material which is an insulating material,
the gate insulating layer of the select transistor comprises the second material, and
the channel layer is disposed between the gate insulating layer and the insulating layer.

2. The semiconductor memory device according to claim 1 , wherein the first material is a transition metal oxide.

3. The semiconductor memory device according to claim 1 , wherein
the first material is a semiconductor oxide, the semiconductor oxide comprising at least one of titanium oxide, zinc oxide, or indium oxide.

4. The semiconductor memory device according to claim 1 , wherein positions of at least one of a source electrode or a drain electrode of the select transistor and a gate electrode of the select transistor in the third direction are partially overlapped.

5. A semiconductor memory device, comprising:
a substrate comprising a surface extending in a first direction and a second direction intersecting the first direction; and
a memory cell array disposed above the substrate, the memory cell array comprising: a first wiring line extending in the first direction, a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; and a select transistor comprising a channel layer and provided between the second wiring line and the third wiring line,
wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select transistor comprises the first material,
the memory cell further comprises a second layer,
the select transistor further comprises a gate insulating layer,
the second layer of the memory cell comprises a second material which is an insulating material,
the gate insulating layer of the select transistor comprises the second material, and
the second material comprises at least one of aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide.

6. A semiconductor memory device, comprising:
a substrate comprising a surface extending in a first direction and a second direction intersecting the first direction; and
a memory cell array disposed above the substrate, the memory cell array comprising: a first wiring line extending in the first direction, a second wiring line extending in a third direction intersecting the first and second directions, a third wiring line extending in the second direction; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; and a select transistor comprising a channel layer and provided between the second wiring line and the third wiring line, wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select transistor comprises the first material,
the second wiring line comprises a third material which is a conductive material, and
at least one of a source electrode or a drain electrode of the select transistor comprises a fourth material, the fourth material being a conductive material and having an electronegativity which is different from that of the third material.

7. The semiconductor memory device according to claim 6 , wherein the fourth material has an electronegativity which is smaller than that of the third material.

8. A semiconductor memory device, comprising:
a memory cell array disposed above a substrate, the memory cell array comprising: a first wiring line and a second wiring line that intersect each other; a third wiring line; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; a select transistor comprising a channel layer and provided between the second wiring line and the third wiring line; and an insulating layer disposed between an end of the second wiring line and the third wiring line,
wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select transistor comprises the first material
the memory cell further comprises a second layer,
the select transistor further comprises a gate insulating layer,
the second layer of the memory cell comprises a second material which is an insulating material,
the gate insulating layer of the select transistor comprises the second material, and
the channel layer is disposed between the gate insulating layer and the insulating layer.

9. The semiconductor memory device according to claim 8 , wherein the first material is a transition metal oxide.

10. The semiconductor memory device according to claim 8 , wherein the first material is at least one of titanium oxide, zinc oxide, or indium oxide.

11. A semiconductor memory device, comprising:
a memory cell array disposed above a substrate, the memory cell array comprising: a first wiring line and a second wiring line that intersect each other; a third wiring line; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; and a select transistor comprising a channel layer and provided between the second wiring line and the third wiring line,
wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select transistor comprises the first material,
the memory cell further comprises a second layer,
the select transistor further comprises a gate insulating layer,
the second layer of the memory cell comprises a second material which is an insulating material,
the gate insulating layer of the select transistor comprises the second material, and
the second material is at least one of aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide.

12. The A semiconductor memory device, comprising:
a memory cell array disposed above a substrate, the memory cell array comprising: a first wiring line and a second wiring line that intersect each other; a third wiring line; a memory cell comprising a first layer and provided in an intersection region of the first wiring line and the second wiring line; and a select transistor comprising a channel layer and provided between the second wiring line and the third wiring line,
wherein
the first layer of the memory cell comprises a first material which is an oxide,
the channel layer of the select

Assignees

• Toshiba Memory Corp

Inventors

• Kabuyanagi Shoichi
• Saitoh Masumi
• Yamaguchi Marina
• Tachikawa Takashi

Classifications

• H01L45/1226

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic