Array substrate and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-10050061-B2
Application number	US-201314402266-A
Country	US
Kind code	B2
Filing date	Dec 10, 2013
Priority date	Sep 18, 2013
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

An array substrate, a manufacturing method of the array substrate and a display device including the array substrate are disclosed. The array substrate includes a substrate ( 1 ), a common electrode layer ( 401 ) located on the substrate ( 1 ) and a conductive layer ( 2 ) provided on a surface of the substrate ( 1 ), the conductive layer ( 2 ) and the common electrode layer ( 401 ) are electrically connected in parallel. The common electrode and the conductive layer are formed into a parallel structure, so that the resistance can be decreased, and in turn, crosstalk, greenish and other phenomenon of the array substrate are reduced, thereby promoting the picture quality of the display device.

First claim

The invention claimed is:

1. An array substrate, comprising: a substrate, a common electrode layer located on the substrate, a conductive layer lying in a different layer from the common electrode layer and a gate electrode located in a different layer from the conductive layer, the conductive layer and the common electrode layer being electrically connected in parallel, and the conductive layer overlapping with a pixel electrode within a pixel region in a direction perpendicular to the substrate;
wherein the conductive layer is formed of a transparent conductive material;
wherein the conductive layer is provided at a surface of the substrate, and the common electrode layer is located above the conductive layer;
wherein the array substrate further comprises: an insulating layer, a gate insulating layer, an active layer, a source electrode and a drain electrode, a first passivation layer, and a second passivation layer;
wherein the conductive layer, the insulating layer, the gate electrode, the gate insulating layer, the active layer, the source electrode and drain electrode, the first passivation layer, the pixel electrode, the second passivation layer, and the common electrode layer are sequentially provided on the substrate;
wherein the conductive layer and the common electrode layer are electrically connected through a via hole in the insulating layer, the first passivation layer, and the second passivation layer.

2. The array substrate claimed as claim 1 , wherein the conductive layer is electrically connected to the common electrode layer through a common electrode metal line.

3. The array substrate claimed as claim 1 , wherein a projection area of the conductive layer upon the substrate does not overlap with a projection area of the gate electrode upon the substrate.

4. A display device, comprising the array substrate claimed as claim 1 .

5. The array substrate claimed as claim 1 , wherein
the common electrode layer is located at a side of the pixel electrode far away from the substrate.

6. The array substrate claimed as claim 1 , wherein
the common electrode layer is electrically connected with the conductive layer through two via holes.

7. A manufacturing method of an array substrate, comprising:
forming a conductive layer lying on a substrate;
forming a gate electrode on a side of the conductive layer far away from the substrate;
forming a common electrode layer on the conductive layer;
forming the conductive layer at a surface of the substrate;
forming an insulating layer on the conductive layer;
forming a gate electrode on the insulating layer;
forming a gate insulating layer on the gate electrode;
forming an active layer on the gate insulating layer;
forming a source electrode and a drain electrode on the active layer;
forming a first passivation layer on the source electrode and the drain electrode;
forming a pixel electrode on the first passivation layer;
forming a second passivation layer on the pixel electrode;
forming the common electrode layer on the second passivation layer;
wherein the conductive layer and the common electrode layer are electrically connected through a via hole
wherein the conductive layer and the common electrode layer are electrically connected in parallel, and the conductive layer overlaps with a pixel electrode within a pixel region in a direction perpendicular to the substrate;
the conductive layer is formed of a transparent conductive material.

8. The manufacturing method claimed as claim 7 , wherein the conductive layer and the common electrode layer are electrically connected through a common electrode metal line.

9. The manufacturing method claimed as claim 7 , wherein a region upon the substrate where the conductive layer is formed does not overlap with a projection area of the gate electrode upon the substrate.

10. An array substrate, comprising: a substrate, a common electrode layer located on the substrate and a conductive layer lying in a different layer from the common electrode layer;
wherein the conductive layer is formed of a metal, and the conductive layer and the common electrode layer being electrically connected in parallel;
the array substrate further comprises a display region and a non-display region, the display region is located in a middle portion of the array substrate and comprises a plurality of pixel units, each pixel unit comprises a pixel electrode and a common electrode, the non-display region is located along a periphery of the display region, and the conductive layer is disposed in the non-display region;
wherein the conductive layer is provided at a surface of the substrate, and the common electrode layer is located above the conductive layer;
wherein the array substrate further comprises: an insulating layer, a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, a first passivation layer, and a second passivation layer;
wherein the conductive layer, the insulating layer, the gate electrode, the gate insulating layer, the active layer, the source electrode and drain electrode, the first passivation layer, the pixel electrode, the second passivation layer, and the common electrode layer are sequentially provided on the substrate;
wherein the conductive layer and the common electrode layer are electrically connected through a via hole in the insulating layer, the first passivation layer, and the second passivation layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Yuanbo
• Qin Wei
• Han Seung Woo
• Ma Ruoyu

Classifications

• H01L27/124 Primary

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title