Semiconductor device and manufacturing method thereof

US10050056B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10050056-B2
Application numberUS-201715821435-A
CountryUS
Kind codeB2
Filing dateNov 22, 2017
Priority dateMay 4, 2016
Publication dateAug 14, 2018
Grant dateAug 14, 2018

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A manufacturing method for a semiconductor device, comprising: alternately stacking first layers and second layers; forming a hole passing through the first layers and the second layers; forming a buffer layer over a sidewall of the hole; curing dangling bonds in the buffer layer to form a first densified area in the buffer layer; forming a data storage layer over the first densified area; and forming a channel layer over the data storage layer, wherein curing is controlled such that a non-densified area is defined in the buffer layer between the first densified area and the sidewall of the hole.

Assignees

Inventors

Classifications

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • of treatments performed after formation of the materials · CPC title

  • to change the surface groups of the insulating materials · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10050056B2 cover?
Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer …
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 14 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).