Method of producing an optoelectronic component and optoelectronic component

US10049967B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10049967-B2
Application numberUS-201615737525-A
CountryUS
Kind codeB2
Filing dateJun 16, 2016
Priority dateJun 19, 2015
Publication dateAug 14, 2018
Grant dateAug 14, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of producing an optoelectronic component includes providing a lead frame having an upper side including a contact region and a chip reception region raised relative to the contact region; arranging an electrically conductive element on the contact region; embedding the lead frame in a molded body, wherein the contact region is covered by the molded body, and the chip reception region and the electrically conductive element remain accessible on an upper side of the molded body; arranging an optoelectronic semiconductor chip on the chip reception region; and connecting the optoelectronic semiconductor chip and the electrically conductive element by a bonding wire.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of producing an optoelectronic component comprising: providing a lead frame having an upper side comprising a contact region and a chip reception region raised relative to the contact region; arranging an electrically conductive element on the contact region; embedding the lead frame in a molded body, wherein the contact region is covered by the molded body, and the chip reception region and the electrically conductive element remain accessible on an upper side of the molded body; arranging an optoelectronic semiconductor chip on the chip reception region; and connecting the optoelectronic semiconductor chip and the electrically conductive element by a bonding wire. 2. The method according to claim 1 , wherein the electrically conductive element is arranged on the contact region such that it protrudes beyond the chip reception region, and the electrically conductive element is pressed flat before the embedding of the lead frame in the molded body such that the electrically conductive element has the same height as the chip reception region. 3. The method according to claim 2 , wherein pressing the electrically conductive element flat is carried out by a closure pressure of a molding tool. 4. The method according to claim 1 , wherein the electrically conductive element is arranged in a recess provided in the contact region. 5. The method according to claim 1 , wherein the electrically conductive element is fixed on the contact region by an electrically conductive bonding medium. 6. The method according to claim 1 , wherein the lead frame is provided having a first lead frame section and a second lead frame section, an electrically conductive element is respectively arranged on the upper side of the first lead frame section and on the upper side of the second lead frame section, and the two electrically conductive elements connect to the optoelectronic semiconductor chip via bonding wires. 7. The method according to claim 1 further comprising: arranging a protective chip on the upper side of the lead frame, the protective chip being embedded in the molded body. 8. An optoelectronic component comprising a carrier and an optoelectronic semiconductor chip, wherein the carrier comprises a lead frame embedded in a molded body, the lead frame comprises an upper side having a contact region and a chip reception region raised relative to the contact region, an electrically conductive element is arranged on the contact region, the contact region is covered by the molded body, the chip reception region and the electrically conductive element are accessible on an upper side of the molded body, and the optoelectronic semi-conductor chip is arranged on the chip reception region and connects to the electrically conductive element by a bonding wire. 9. The optoelectronic component according to claim 8 , wherein the chip reception region is flush with a section of the upper side of the molded body. 10. The optoelectronic component according to claim 8 , wherein the chip reception region has an undercut at the boundary with the contact region. 11. The optoelectronic component according to claim 8 , wherein the molded body forms a cavity on its upper side, and the optoelectronic semiconductor chip is arranged in the cavity. 12. The optoelectronic component according to claim 8 , wherein the lead frame is accessible on a lower side, lying opposite the upper side, of the molded body. 13. The optoelectronic component according to claim 8 , wherein the optoelectronic component comprises a further optoelectronic semiconductor chip. 14. The optoelectronic component according to claim 13 , wherein the lead frame comprises a further chip reception region raised relative to the contact region, and the further optoelectronic semiconductor chip is arranged on the further chip reception region.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

  • H10W70/421Primary

    Shapes or dispositions · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10049967B2 cover?
A method of producing an optoelectronic component includes providing a lead frame having an upper side including a contact region and a chip reception region raised relative to the contact region; arranging an electrically conductive element on the contact region; embedding the lead frame in a molded body, wherein the contact region is covered by the molded body, and the chip reception region a…
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 14 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).