Through-substrate vias and methods for forming the same

Patent metadata

Field	Value
Publication number	US-10049965-B2
Application number	US-201414325727-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Apr 27, 2012
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate;
a Metal-Oxide-Semiconductor (MOS) transistor comprising:
a gate electrode over the semiconductor substrate; and
a source/drain region on a side of the gate electrode;

a source/drain contact plug comprising a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is over and electrically connected to the source/drain region;
a gate contact plug over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the upper portion of the source/drain contact plug, and the gate contact plug comprises a continuous sidewall extending from a top surface of the gate electrode to a level coplanar with the top surface of the upper portion of the source/drain contact plug;
a first via and a first metal line over the first via, wherein the first via and the first metal line form a first dual damascene structure, and a bottom surface of the first via is in contact with a top surface of the gate contact plug; and
a Through-Substrate Via (TSV) extending into the semiconductor substrate, wherein a top surface of the TSV is substantially level with a top surface of the first metal line.

2. The device of claim 1 further comprising:
an Inter-Layer Dielectric (ILD) over the semiconductor substrate, wherein the gate electrode and the lower portion of the source/drain contact plug comprise portions in the ILD; and
an etch stop layer over and contacting the ILD, wherein the upper portion and the lower portion of the source/drain contact plug have an interface substantially level with a bottom surface of the etch stop layer.

3. The device of claim 2 , wherein the upper portion of the source/drain contact plug extends through the etch stop layer.

4. The device of claim 1 , wherein in a cross-sectional view of the device, the first via is laterally narrower than the first metal line.

5. The device of claim 1 , wherein the TSV comprises:
an insulation layer in contact with the semiconductor substrate;
a diffusion barrier layer over the insulation layer; and
a metallic material over the diffusion barrier layer, wherein each of the insulation layer, the diffusion barrier layer, and the metallic material extends from the top surface of the first metal line into the semiconductor substrate.

6. The device of claim 1 further comprising an etch stop layer over the gate contact plug and the source/drain contact plug, wherein a bottom surface of the etch stop layer is in physical contact with top surfaces of both the gate contact plug and the source/drain contact plug.

7. The device of claim 1 further comprising a second via and a second metal line over the second via, wherein the second via and the second metal line form a second dual damascene structure, and a bottom surface of the second via is in contact with a top surface of the source/drain contact plug.

8. The device of claim 1 further comprising a Shallow Trench Isolation (STI) region, with substantially an entirety of the STI region in the semiconductor substrate, wherein the TSV penetrates through the STI region.

9. A device comprising:
a semiconductor substrate;
a Metal-Oxide-Semiconductor (MOS) transistor comprising:
a gate electrode over the semiconductor substrate; and
a source/drain region with a portion in the semiconductor substrate;

a first Inter-Layer Dielectric (ILD) over the source/drain region, wherein the first ILD has a top surface coplanar with a top surface of the gate electrode;
an etch stop layer over and contacting the first ILD;
a second ILD over and contacting the etch stop layer;
a gate contact plug having a bottom surface contacting a top surface of the gate electrode, and a top surface coplanar with a top surface of the second ILD;
a via and a metal line over the via, wherein the via and the metal line form a dual damascene structure, and a bottom surface of the via physically contacts a top surface of the gate contact plug;
a Through-Substrate Via (TSV) extending into the semiconductor substrate, wherein a top surface of the TSV is substantially level with a top surface of the metal line; and
a Shallow Trench Isolation (STI) region in the semiconductor substrate, with a top surface of the STI region coplanar with a top surface of the semiconductor substrate, and wherein the TSV penetrates through the STI region.

10. The device of claim 9 , wherein the dual damascene structure comprises a diffusion barrier layer continuously extending from a top surface of the metal line to a bottom surface of the via.

11. The device of claim 9 , wherein the gate contact plug laterally extend beyond an edge of the gate electrode.

12. The device of claim 11 further comprising an additional etch stop layer comprising a bottom surface contacting the top surface of the gate contact plug.

13. The device of claim 11 further comprising a source/drain contact plug electrically connected to a source/drain region of the MOS transistor, wherein the source/drain contact plug comprises:
a lower portion in the first ILD; and
an upper portion in the second ILD and the etch stop layer, wherein the lower portion and the upper portion of the source/drain contact plug have a distinguishable interface.

14. The device of claim 13 , wherein a bottom surface of the via is at substantially a same level as a top surface of the upper portion of the source/drain contact plug source/drain contact plug.

15. The device of claim 9 , wherein the gate contact plug comprises a straight sidewall extending from the bottom surface to the top surface of the gate contact plug.

16. The device of claim 9 , wherein in a cross-sectional view of the device, the via is laterally narrower than the metal line.

17. A device comprising:
a semiconductor substrate;
a Metal-Oxide-Semiconductor (MOS) transistor comprising:
a gate electrode over the semiconductor substrate; and
a source/drain region with a portion in the semiconductor substrate;

a first Inter-Layer Dielectric (ILD) over the semiconductor substrate;
an etch stop layer over and contacting the first ILD;
a second ILD over and contacting the etch stop layer;
a gate contact plug having a bottom surface contacting a top surface of the gate electrode, and a top surface coplanar with a top surface of the second ILD, wherein the gate contact plug laterally extends beyond an edge of the gate electrode;
a Shallow Trench Isolation (STI) region extending into the semiconductor substrate;
a via and a metal line over the second ILD, wherein the via and the metal line form a dual damascene structure, and a bottom surface of the via physically contacts a top surface of the gate contact plug; and
a Through-Substrate Via (TSV) extending penetrating through the STI region, wherein a top surface of the TSV is substantially level with a top surface of the metal line.

18. The device of claim 17 , wherein the gate contact plug comprises a straight sidewall extending from a first level to a second level, with the first level being coplanar with the top surface of the gate contact plug, and the second level being coplanar with the top surface of the second ILD.

19. The device of claim 17 , wherein a bottom surface of the via is coplanar with a top surface of the second ILD.

20. The device of claim 17 , wherein in a cross-sectional view of the device, the via is laterally narrower than the metal line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ming-Fa
• Wang Yu-Young
• Jan Sen-Bor

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title