Method of planarizing substrate surface

Patent metadata

Field	Value
Publication number	US-10049887-B2
Application number	US-201715678117-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Jul 5, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

First claim

What is claimed is:

1. A method of planarizing a substrate surface, comprising:
providing a substrate having a major surface of a material layer, wherein the major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate;
depositing a polish stop layer on the major surface of the material layer;
depositing a cap layer on the polish stop layer;
forming a photoresist pattern on the cap layer, wherein the photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate;
etching away at least a portion of the cap layer not covered by the photoresist pattern; and
removing the photoresist pattern.

2. The method according to claim 1 , wherein the material layer comprises amorphous silicon.

3. The method according to claim 1 , wherein the polish stop layer comprises silicon nitride.

4. The method according to claim 3 , wherein the cap layer comprises silicon oxide or amorphous silicon.

5. The method according to claim 1 , wherein after removing the photoresist pattern, the method further comprises:
performing a chemical mechanical polishing (CMP) process to polish the cap layer.

6. The method according to claim 5 , wherein after performing the CMP process to polish the cap layer, the method further comprises:
performing a dry etching process to etch the cap layer, the polishing stop layer, and the material layer.

7. The method according to claim 1 , wherein after depositing the cap layer on the polish stop layer and before forming the photoresist pattern on the cap layer, the method further comprises:
performing a chemical mechanical polishing (CMP) process to polish the cap layer.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Li-Chieh
• Tsai Fu-Shou
• Li Yu-Ting
• Liu Yi-Liang
• Li Kun-Ju

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H01L21/31053 Primary

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic