Method for growing epitaxies of a chemical compound semiconductor

Patent metadata

Field	Value
Publication number	US-10049872-B2
Application number	US-201615063572-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Mar 17, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.

First claim

What is claimed is:

1. A method comprising:
providing a substrate;
forming a prelayer over the substrate;
forming a barrier layer over the prelayer; and
forming, over the barrier layer, a channel layer that includes (i) a pair of layers, of common composition, that include AlGa, and (ii) an InAs layer, of different composition than the pair of layers, sandwiched between the pair of layers.

2. The method of claim 1 , wherein forming the channel layer is performed using a metal organic chemical vapor deposition (MOCVD).

3. The method of claim 1 , wherein the pair of layers include Sb.

4. The method of claim 1 , further comprising fabricating a transistor that includes the channel layer.

5. A method comprising:
providing a substrate;
forming a prelayer over the substrate;
forming a barrier layer over the prelayer; and
forming, over the barrier layer, a channel layer that includes (i) a pair of layers, of common composition, that include Al, and (ii) an InGaAs layer, of different composition than the pair of layers, sandwiched between the pair of layers.

6. The method of claim 5 , wherein the pair of layers include Sb.

7. The method of claim 5 , wherein the pair of layers include In.

8. The method of claim 5 , further comprising fabricating a transistor that includes the channel layer.

9. The method of claim 5 , wherein forming the channel layer is performed using a metal organic chemical vapor deposition (MOCVD).

10. A method comprising:
providing a substrate;
forming a prelayer over the substrate;
forming a barrier layer, consisting of GaAs, over the prelayer; and
forming, over the barrier layer, a channel layer that includes (i) a pair of layers, of common composition, that include Sb, and (ii) an InAs layer, of different composition than the pair of layers, sandwiched between the pair of layers.

11. The method of claim 10 , wherein the pair of layers include Al.

12. The method of claim 10 , wherein the pair of layers include In.

13. The method of claim 10 , further comprising fabricating a transistor that includes the channel layer.

14. The method of claim 10 , wherein forming the channel layer is performed using a metal organic chemical vapor deposition (MOCVD).

15. The method of claim 5 , wherein the pair of layers include AlInSb.

16. The method of claim 5 , wherein the pair of layers include AlGaSb.

17. The method of claim 10 , wherein the pair of layers include AlInSb.

18. The method of claim 10 , wherein the pair of layers include InSb.

19. The method of claim 16 , wherein the substrate is a Ge substrate.

20. The method of claim 19 , wherein the prelayer is a graded-temperature arsenic prelayer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ National Chiao Tung
• Taiwan Semiconductor Manufacturing Company Limited & National Chiao Tung Univ

Inventors

• Yu Hung-Wei
• Chang Yi
• Wang Tsun-Ming

Classifications

• H10P14/3422

  Antimonides · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3221

  Arsenides · CPC title