Multilayer capacitor with integrated busbar

Patent metadata

Field	Value
Publication number	US-10049819-B2
Application number	US-201615378722-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Jan 30, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Embodiments are directed to obtaining a specification of at least one operational requirement for at least one capacitor, generating a design of the at least one capacitor to satisfy the at least one operational requirement, the design of the at least one capacitor comprising a plurality of layers and a first integrated busbar coupled to at least a portion of the layers, and based on the design, manufacturing the at least one capacitor by utilizing an additive manufacturing technique.

First claim

What is claimed is:

1. A capacitor manufactured by application of an additive manufacturing technique, comprising:
a plurality of conductor layers;
a plurality of dielectric layers interspersed between the conductor layers; and
a first busbar comprising a first terminal at an exterior of the capacitor, the first busbar being directly coupled to a first subset of the conductor layers and the first subset comprising at least two conductor layers which are unconnected to each other except through the first busbar; and
a second busbar comprising a second terminal at an exterior of the capacitor, the second busbar being directly coupled to a second subset of the conductor layers different than the first subset and the second subset comprising at least two conductor layers which are unconnected to each other except through the second busbar.

2. The capacitor of claim 1 , wherein:
the first busbar and the first terminal extend transversely relative to the first subset of conductor layers,
the second busbar and the second terminal extend transversely relative to the second subset of conductor layers, and
the first and second subsets of conductor layers respectively extend outwardly from opposing sides of the first and second busbars and are interleaved with respect to one another.

3. The capacitor of claim 1 , wherein the dielectric layers are made of polyimide, and wherein the conductor layers are made of a graphite oxide material.

4. The capacitor of claim 1 , wherein the first busbar is configured to couple to a second busbar located on an assembly.

5. The capacitor of claim 1 , wherein the capacitor is manufactured in accordance with a direct write technology.

6. The capacitor of claim 1 , wherein the capacitor is manufactured in accordance with a laser engineered net shaping technique.

7. A capacitor, comprising:
a body;
a first busbar comprising a first terminal supportively disposed within the body such that the first terminal extends outwardly from the body;
a second busbar comprising a second terminal supportively disposed within the body such that the second terminal extends outwardly from the body;
first conductor layers extending through the body and toward the second busbar from a side of the first busbar facing the second busbar;
second conductor layers extending through the body and toward the first busbar from a side of the second busbar facing the first busbar,
the first and second conductor layers being interleaved with one another; and
dielectric material provided in layers interposed between sequential first and second conductor layers and as hairpin sections interposed between respective ends of the first and second conductor layers and the second and first busbars, respectively.

8. The capacitor according to claim 7 , wherein the first and second terminals respectively comprise voltage buses.

9. The capacitor according to claim 7 , wherein the first and second busbars and the first and second terminals are substantially parallel with each other and transversely oriented relative to the first and second conductor layers and the layers of the dielectric material.

10. The capacitor according to claim 7 , wherein the first and second busbars and the first and second terminals are substantially parallel with each other and perpendicular relative to the first and second conductor layers and the layers of the dielectric material.

11. The capacitor according to claim 10 , wherein the hairpin sections of the dielectric material form 180° angles about the respective ends of the first and second conductor layers.

12. The capacitor according to claim 10 , wherein the dielectric material comprises polyimide and the first and second conductor layers comprise graphite oxide.

Assignees

• Hamilton Sundstrand Corp

Inventors

• Horowy John
• Galloway Gary L
• Pal Debabrata
• Karlen Eric
• Metzler Mark W

Classifications

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title

• H01G2/04

  specially adapted for mounting on a chassis · CPC title