Memory circuit with a bistable circuit and a non-volatile element

Patent metadata

Field	Value
Publication number	US-10049740-B2
Application number	US-201515501247-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Aug 12, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

First claim

The invention claimed is:

1. A memory circuit comprising:
a plurality of cells arranged in a plurality of rows and a plurality of columns so that the plurality of rows are grouped to form a plurality of banks each including one or more rows, each of the plurality of cells including: a bistable circuit configured to store data; and a non-volatile element configured to store data stored in the bistable circuit in a non-volatile manner and to restore data stored in a non-volatile manner to the bistable circuit; and
a controller configured to:
perform a store operation on each of the plurality of rows in turn;
set a voltage supplied, as a power-supply voltage, to cells in a first bank of the plurality of banks to a first voltage, the first bank including a row on which the store operation is performed; and
set a voltage supplied, as a power-supply voltage, to cells in a bank of the plurality of banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

2. The memory circuit according to claim 1 , wherein the controller is configured to sequentially set a voltage supplied, as a power-supply voltage, to the cells in a bank of which all rows have been subject to the store operation to the second voltage among the plurality of banks.

3. The memory circuit according to claim 1 , wherein the controller is configured to sequentially shut down a voltage supplied, as a power-supply voltage, to the cells in a bank of which all rows have been subject to the store operation among the plurality of banks.

4. The memory circuit according to claim 1 , wherein:
the non-volatile element includes a first end coupled to a node in the bistable circuit and a second end coupled to a control line;
each of the plurality of cells includes a switch connected in series to the non-volatile element between the node and the control line; and
a voltage supplied, as a power-supply voltage, to the plurality of cells is supplied to the bistable circuit.

5. The memory circuit according to claim 1 , wherein each of the plurality of banks includes one row.

6. A memory circuit comprising:
a plurality of cells, each including: a bistable circuit configured to store data; and a non-volatile element configured to store data stored in the bistable circuit in a non-volatile manner and to restore data stored in a non-volatile manner to the bistable circuit;
one or more power switches configured to change a voltage supplied, as a power-supply voltage, to the plurality of cells; and
a controller configured to perform a store operation on each of a plurality of blocks at different times in a region, the region to which a same voltage is supplied by a single power switch being divided into the plurality of blocks.

7. The memory circuit according to claim 6 , wherein:
the plurality of cells are arranged in a plurality of rows and a plurality of columns;
the region includes one or more rows; and
one row is divided into the plurality of blocks.

8. The memory circuit according to claim 7 , wherein:
each of the plurality of cells includes a switch for performing storing of data;
the switches in cells of each of the plurality of blocks are coupled to a same sub-switch line;
sub-switch lines in a same row are coupled to a single switch line; and
the memory circuit further comprises a selection circuit configured to select one block of the plurality of blocks, and to output a signal for turning on the switch to a sub-switch line of a selected block.

9. The memory circuit according to claim 8 , wherein:
the non-volatile element includes a first end coupled to a node in the bistable circuit, and a second end coupled to a control line;
the switch is connected in series to the non-volatile element between the node and the control line; and
a voltage supplied, as a power-supply voltage, to the cell is supplied to the bistable circuit.

10. The memory circuit according to claim 7 , wherein each of the plurality of blocks includes consecutive cells in a same row.

11. The memory circuit according to claim 7 , wherein each of the plurality of blocks includes cells periodically arranged in a same row.

12. The memory circuit according to claim 6 , further comprising:
a determination circuit configured to determine whether data in the bistable circuit and data in the non-volatile element match in cells of each of the plurality of blocks; and
a selection circuit configured to perform the store operation of the cells in a corresponding block when the data in the bistable circuit and the date in the no-volatile element fail to match, and not to perform the store operation of the cells in the corresponding block when the data in the bistable circuit and the date in the no-volatile element match.

Assignees

• Japan Science & Tech Agency
• Kanagawa Academy Of Science And Tech
• Kanagawa Institute Of Industrial Science And Tech

Inventors

• Sugahara Satoshi
• SHUTO Yusuke
• Yamamoto Shuichiro

Classifications

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title