Single-sided source and gate driver arrangement for display device

Patent metadata

Field	Value
Publication number	US-10049635-B2
Application number	US-201615185746-A
Country	US
Kind code	B2
Filing date	Jun 17, 2016
Priority date	Dec 20, 2013
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A display device includes source drivers, at least one gate driver, a first substrate, a second substrate, gate lines, source lines, lead-out lines and connection parts, wherein the gate signals are emitted from the gate driver to the gate lines via the lead-out lines and the connection parts, the source drivers include a first source driver and a second source driver, the second source driver being spaced apart from the first source driver in a first direction, and the gate driver is located between the first source driver and second source driver in the first direction.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of source drivers for emitting source signals;
at least one gate driver for emitting gate signals;
a first substrate having a display area for displaying images, the images represented by source signals and gate signals;
a second substrate including a first area overlapping with the first substrate, and a second area on which the plurality of source drivers and the at least one gate driver are attached;
a plurality of gate lines extending in a first direction on the first area;
a plurality of source lines extending in a second direction which is different from the first direction;
a plurality of lead-out lines extending in the second direction;
a plurality of connection parts, each of the plurality of connection parts connecting one of the plurality of lead-out lines to one of the plurality of gate lines;
a plurality of source relay lines for transmitting source signals from the plurality of source drivers to the plurality of source lines;
a plurality of gate relay lines for transmitting gate signals from the gate driver to the plurality of lead-out lines; and
an insulating layer for insulating the plurality of source relay lines from the plurality of gate relay lines, wherein
the gate driver overlaps with at least one of the plurality of source relay lines,
the gate signals are emitted from the gate driver to the plurality of gate lines via the plurality of lead-out lines and the plurality of connection parts,
the plurality of source drivers include a first source driver and a second source driver, the second source driver being spaced apart from the first source driver in the first direction,
the gate driver is located between the first source driver and second source driver in the first direction, and
the gate driver is located closer to the first area than the plurality of source drivers.

2. The display device according to claim 1 , wherein
at least one of the plurality of source relay lines and at least one of the plurality of gate relay lines overlap in the first area.

3. The display device according to claim 1 , wherein
each of the plurality of lead-out lines electrically connects to a respective one of the gate relay lines at one of a plurality of jointing points,
the plurality of gate relay lines include a first gate relay line, and a second gate relay line being shorter than the first gate relay line,
the plurality of lead-out lines include a first lead-out line connecting to the first gate relay line, and a second lead-out line connecting to the second gate relay line,
the plurality of gate lines include a first gate line and a second gate line,
the plurality of connection parts include a first connection part connecting the first lead-out line to the first gate line, and a second connection part connecting the second lead-out line to the second gate line,
the plurality of jointing points include a first jointing point and a second jointing point, the first gate relay line electrically connecting to the first lead-out line at the first jointing point, and the second gate relay line electrically connecting to the second lead-out line at the second jointing point, and
a distance from the first jointing point to the first connection part is shorter than a distance from the second jointing point to the second connection part.

4. The display device according to claim 1 , wherein
the plurality of gate relay lines include a first gate relay line and a second gate relay line,
the plurality of lead-out lines include a first lead-out line connecting to the first gate relay line, and a second lead-out line connecting to the second gate relay line,
the first gate relay line and the first lead-out line transmit gate signals in a first transmission span,
the second gate relay line and the second lead-out line transmit gate signals in a second transmission span being longer than the first transmission span, and
at least a part of the second transmission span has a lower ratio of electric resistance per unit of length than the first transmission span.

5. The display device according to claim 4 , wherein
the second transmission span includes a double-line span, the double-line span having two lines transmitting gate signals in parallel.

6. The display device according to claim 5 , wherein
the first transmission span includes a double-line span, and
the double-line span of the second transmission span is longer than the double-line span of the first transmission span.

Assignees

• Panasonic Liquid Crystal Displ

Inventors

• Kawamura Tetsuya
• Izawa Tetsurou

Classifications

• G09G2340/145

  related to small screens · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3685

  Details of drivers for data electrodes · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title