Interface emulator using FIFOs

Patent metadata

Field	Value
Publication number	US-10049073-B2
Application number	US-201715621265-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Jun 6, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of functional circuit blocks;
an access port configured to couple the integrated circuit to first and second external devices configured to communicate using first and second communications protocols, respectively;
first and second input first-in, first-out memories (FIFOs) coupled to receive data from the first and second external devices, respectively, via the access port, wherein each of the first and second input FIFOs is coupled to provide data to one or more of the plurality of functional circuit blocks; and
first and second output FIFOs coupled to provide data to the first and second external devices, respectively, wherein each of the first and second output FIFOs is coupled to receive data from at least one of the plurality of functional circuit blocks;
wherein the access port, the first FIFO, and the second FIFO comprise first and second communications channels, wherein the first communications channel is configured to emulate an interface according to the first communications protocol during communications involving the first external device, and wherein the second communications channel is configured to emulate an interface according to the second communications protocol during communications involving the second external device.

2. The integrated circuit as recited in claim 1 , wherein the access port is a physical access port configured to provide hardwired connections to at least one of the first and second external devices.

3. The integrated circuit as recited in claim 1 , wherein the access port is configured to provide a wireless connection to at least one of the first and second external devices.

4. The integrated circuit as recited in claim 1 , wherein the access port comprises a debug access port configured to provide a JTAG (Joint Test Action Group) interface to the integrated circuit.

5. The integrated circuit as recited in claim 1 , wherein the access port comprises a serial wire debug (SWD) interface.

6. The integrated circuit as recited in claim 1 , further comprising a first timer associated with a respective one of the input FIFOs and a second timer associated with a respective one of the output FIFOs, wherein the first and second timers are configured to enforce maximum latency requirements.

7. The integrated circuit as recited in claim 1 , wherein the first communications channel is configured to emulate a universal serial bus (USB) port and the second communications channel is configured to emulate a universal asynchronous receiver-transmitter (UART).

8. A method comprising:
conducting communications between internal circuitry of an integrated circuit (IC) and a first external device through a first communications channel emulating a first interface having a first predefined protocol, wherein conducting communications through the first communications channel comprises inputting data to the internal circuitry from the first external device via a first input first-in, first-out memory (FIFO) and outputting data from the internal circuitry to the first external device via a first output FIFO; and
conducting communications between the internal circuitry and a second external device through a second communications channel emulating a second interface having a second predefined protocol, wherein conducting communications through the second communications channel comprises inputting data to the internal circuitry from the second external device via a second input FIFO and outputting data from the internal circuitry to the second external device via a second output FIFO;
wherein conducting communications through the first and second communications channels further comprised conducting communications through an access port coupled to each of the first and second external devices, the first and second input FIFOs, and the first and second output FIFOs.

9. The method as recited in claim 8 , wherein conducting communications through the first communications channel comprises conducting communications through a hardwired connection of the access port.

10. The method as recited in claim 8 , wherein conducting communications through the second communications channel comprises conducting communications through a wireless connection of the access port.

11. The method as recited in claim 8 , wherein conducting communications through the access port comprises conducting communications through a JTAG (Joint Test Action Group) interface implemented on the integrated circuit.

12. The method as recited in claim 8 , wherein conducting communications through the access port comprises conducting communications through a serial wire debug (SWD) interface implemented on the integrated circuit.

13. The method as recited in claim 8 , further comprising at least one or more timers enforcing latency requirements for communications through a correspondingly coupled one of the first and second communications channels.

14. The method as recited in claim 8 , further comprising the first communications channel emulating a universal serial bus (USB) interface, and the second communications channel emulating a universal asynchronous receiver-transmitter (UART) interface.

15. A system comprising:
an integrated circuit having a debug access port (DAP), one or more functional circuits blocks, first and second input FIFOs (first-in, first-out memories) coupled between the DAP and at least one of the functional circuit blocks; and first and second output FIFOs coupled between the DAP and at least one of the functional circuit blocks; and
a docking port coupled to the DAP and configured to be coupled to first and second external devices;
wherein the docking port and the DAP are configured to provide an interface for first and second communications channels with the first and second external devices, respectively, wherein the first communications channel comprises the first input FIFO and the first output FIFO and emulates communications through an interface of a first type in accordance with a first communications protocol, and wherein the second communications channel comprises the second input FIFO and the second output FIFO and emulates communication through an interface of a second type in accordance with a second communications protocol different from the first communications protocol.

16. The system as recited in claim 15 , wherein the first communications channel is configured to emulate a universal serial bus (USB) interface.

17. The system as recited in claim 15 , wherein the second communications channel is configured to emulate a universal asynchronous receiver-transmitter (UART) interface.

18. The system as recited in claim 15 , wherein the docking port is configured to provide a hardwired connection to the first external device.

19. The system as recited in claim 15 , wherein the docking port is configured to provide a wireless interface to the second external device.

20. The system as recited in claim 15 , wherein the debug access port is a JTAG (Joint Test Action Group) port.

Assignees

• Apple Inc

Inventors

• Smith Michael J
• De Cesare Josh P
• Tripathi Brijesh
• Iwamoto Derek
• Keil Shane J

Classifications

• G06F13/105

  where the program performs an input/output emulation function · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4059

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title