Systems and methods for analyzing stability using metal resistance variations

Patent metadata

Field	Value
Publication number	US-10048939-B2
Application number	US-201414907423-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Aug 28, 2013
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

First claim

What is claimed is:

1. A method for generating a digital value for a physically unclonable function, the method comprising:
receiving a first voltage value;
receiving a second voltage value;
generating a thermometer code, wherein the thermometer code includes a number of consecutive bits of a first bit value and wherein the number of consecutive bits of a first value is proportional to a magnitude of a voltage difference between the first voltage value and the second voltage value; and in which generating a thermometer code includes one of:
(i) applying a voltage corresponding to the first voltage value to even numbered inverters in an inverter chain and applying a voltage corresponding to the second voltage value to odd numbered inverters in the inverter chain; or
(ii) applying a first edge associated with the first voltage to a first delay chain and applying a second edge associated with the second voltage to a second delay chain, wherein the second edge trails the first edge by a predetermined value.

2. The method according to claim 1 , wherein receiving a voltage value includes receiving a voltage value corresponding to an entropy source, wherein the entropy source includes a passive conductor included in an integrated circuit.

3. The method according to claim 2 , wherein the passive conductor includes one of: metal wires, silicided polysilicon, unsilicided polysilicon, ndiffusion, pdiffusion, newel, or dwell.

4. The method according to claim 2 , wherein receiving the first voltage value includes receiving a voltage value corresponding to a first metal layer of an integrated circuit power grid and receiving the second voltage value includes receiving a voltage value corresponding to a second metal layer of the integrated circuit power grid, wherein the first metal layer and the second metal layer are consecutive metal layers.

5. The method according to claim 1 , wherein generating a thermometer code includes (i) applying a voltage corresponding to the first voltage value to even numbered inverters in an inverter chain and applying a voltage corresponding to the second voltage value to odd numbered inverters in the inverter chain; and wherein generating a thermometer code further comprises at each inverter output in the inverter chain storing a bit value of one or zero in a respective latch based on whether a pulse is detected.

6. The method according to claim 1 , wherein generating a thermometer code includes (ii) applying a first edge associated with the first voltage to a first delay chain and applying a second edge associated with the second voltage to a second delay chain, wherein the second edge trails the first edge by a predetermined value; and wherein generating a thermometer code further comprises at each stage of the delay chain storing a bit value of one or zero in a respective latch based on an order of an output of first delay chain or a corresponding output of the second delay is applied to the respective latch.

7. The method according to claim 1 , wherein generating a thermometer code includes eliminating transistor current variations associated with the first voltage value and the second voltage value.

8. The method according to claim 1 , further comprising generating two or more redundant thermometer codes and determining a final thermometer code based on a majority rule.

9. A device for generating a digital value for a physically unclonable function, the device comprising:
a first input for receiving a first voltage value;
a second input for receiving a second voltage value; and
circuitry configured to generate a thermometer code, wherein the thermometer code includes a number of consecutive bits of a first bit value and where the number of consecutive bits of a first value is proportional to a magnitude of a voltage difference between the first voltage value and the second voltage value; and in which the circuitry configured to generate a thermometer code includes one of:
(i) an inverter chain and wherein a voltage corresponding to the first voltage value is applied to even numbered inverters in the inverter chain and a voltage corresponding to the second voltage value is applied to odd numbered inverters in the inverter chain; or
(ii) circuitry configured to apply a first edge associated with the first voltage to a first delay chain and apply a second edge associated with the second voltage to a second delay chain, wherein the second edge trails the first edge by a predetermined time value.

10. The device of claim 9 , wherein a voltage value includes receiving a voltage value corresponding to an entropy source, wherein the entropy source includes a passive conductor included in an integrated circuit.

11. The device of claim 10 , wherein the passive conductor includes one of: metal wires, silicided polysilicon, unsilicided polysilicon, ndiffusion, pdiffusion, nwell, or pwell.

12. The device of claim 10 , wherein the first voltage value includes a voltage value corresponding to a first metal layer of an integrated circuit power grid and wherein the second voltage value includes a voltage value corresponding to a second metal layer of the integrated circuit power grid, wherein the first metal layer and the second metal layer are consecutive metal layers.

13. The device of claim 9 , wherein the circuitry configured to generate a thermometer code includes (i) an inverter chain and wherein a voltage corresponding to the first voltage value is applied to even numbered inverters in the inverter chain and a voltage corresponding to the second voltage value is applied to odd numbered inverters in the inverter chain; and wherein the circuitry configured to generate a thermometer code further includes respective latches operably coupled to each inverter output in the inverter chain, wherein the respective latches are configured to store a bit value of one or zero based on whether a pulse is detected.

14. The device of claim 9 , wherein the circuitry configured to generate a thermometer code includes (ii) circuitry configured to apply a first edge associated with the first voltage to a first delay chain and apply a second edge associated with the second voltage to a second delay chain, wherein the second edge trails the first edge by a predetermined time value and wherein the circuitry configured to generate a thermometer code includes respective latches operably coupled to each stage output in the delay chain and a bit value of one or zero is stored in each of the respective latches based on an order of which an output of first delay chain or a corresponding output of the second delay is applied to a respective latch.

15. The device of claim 9 , wherein generating a thermometer code includes eliminating transistor current variations associated with the first voltage value and the second voltage value.

16. The device of claim 9 , further comprising generating two or more redundant thermometer codes and determining a final thermometer code based on a majority rule.

Assignees

• Stc Unm

Inventors

• Plusquellic James

Classifications

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• H04L2209/26

  Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title