Detector circuit

Patent metadata

Field	Value
Publication number	US-10048300-B2
Application number	US-201414261466-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Apr 25, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A device comprises a multiplication circuit configured to derive a product of a first signal S1 and a second signal S2, S2 having a phase difference β relative to the first signal S1, a low pass filter configured to remove a selected frequency component from the product of S1 and S2 to derive a dot product S1•S2; and a calculation circuit configured to receive the dot product S1•S2 and generate a signal output having a ratio |S1|/|S2| and the phase difference β.

First claim

What is claimed is:

1. A device, comprising:
a sensing impedance Z sense ;
an impedance Z x connected in a series connection with the sensing impedance Z sense ;
a multiplication circuit configured to derive a signal representing a product of a first signal S 1 received at a first signal input and a second signal S 2 received at a second signal input, S 2 having a phase difference β relative to the first signal S 1 , wherein the first signal S 1 is a voltage V 10 across the series connection of the sensing impedance Z sense and the impedance Z x wherein the second signal S 2 is a voltage V 12 across the sensing impedance Z sense , and a third signal S 3 received at a third signal input is a voltage Y 20 across the impedance Z x , and wherein the third signal S 3 has a phase difference α relative to the first signal S 1 ;
a low pass filter configured to remove a selected frequency component from the signal representing the product of S 1 and S 2 to provide an output signal substantially proportional to a dot product S 1 •S 2 ; and
a calculation circuit configured to receive the output signal substantially proportional to the dot product S 1 •S 2 and generate a signal output having a ratio |S 1 |/|S 2 | and the phase difference β.

2. The device of claim 1 , wherein the multiplication circuit and the low pass filter are configured to derive three dot-products S 1 •S 2 , S 2 •S 3 , and S 1 •S 3 .

3. The device of claim 2 , further comprising a feedback network configured to generate a ratio of two of the dot products S 1 •S 2 , S 2 •S 3 , and S 1 •S 3 .

4. The device of claim 1 , further comprising three subtraction circuits configured to derive V 10 and V 12 from three input potentials P 0 , P 1 , P 2 .

5. The device of claim 1 , wherein the multiplication circuit further comprises:
two (2) double balanced mixers or Gilbert cells and a capacitance configured to generate a differential output voltage that represents a difference of the dot product S 1 •S 2 and another dot product based on the third signal S 3 ;
a comparator configured to receive the differential output voltage and generate an up/down signal; and
an up-down-counter responsive to the up/down signal and configured to control at least one of the two (2) double balanced mixers or Gilbert cells.

6. The device of claim 1 , wherein the signal output is configured to provide:
ratios |V 10 |/|V 12 |, |V 12 |/|V 20 |, |V 20 |/|V 10 |;
a measure for the phase difference φ between V 12 and V 10 ;
a measure for the phase difference ψ between V 20 and V 10 ; and
a measure for the phase difference γ between V 20 and V 12 .

7. The device of claim 1 , wherein the device is an impedance detector.

8. A device, comprising:
a multiplication circuit configured to receive a first signal S 1 and a second signal S 2 having a phase difference β relative to the first signal S 1 , the multiplication circuit comprising two double balanced mixers or Gilbert cells, a comparator, and an up-down-counter, the double balanced mixers or Gilbert cells and a capacitance configured to generate a differential output voltage representing a difference of a first dot product S 1 •S 2 and another dot product based on a third signal S 3 received by the multiplication circuit, the comparator configured to receive the differential output voltage and generate an up/down signal, the up-down-counter responsive to the up/down signal and configured to control at least one of the double balanced mixers or Gilbert cells;
a low pass filter configured to remove a selected frequency component from a product of S 1 and S 2 to derive a signal representing the first dot product S 1 •S 2 ; and
a calculation circuit configured to receive the signal representing the first dot product S 1 •S 2 and generate a signal output having a ratio |S 1 |/|S 2 | and the phase difference β.

9. The device of claim 8 , wherein:
the first signal S 1 is a voltage V 10 across a serial connection of a sensing impedance Z sense and an impedance Z x ; and
the second signal S 2 is a voltage V 12 across the sensing impedance Z sense .

10. The device of claim 9 , wherein:
the multiplication circuit is configured to receive the third signal S 3 ;
the third signal S 3 is a voltage V 20 across the impedance Z x ; and
the third signal S 3 has a phase difference α relative to the first signal S 1 .

Assignees

• Qualcomm Inc
• Qualcomm Technologies Inc

Inventors

• Van Der Cammen Peter

Classifications

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• G01R27/02 Primary

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title