Complementary current reusing preamp for operational amplifier

Patent metadata

Field	Value
Publication number	US-10044362-B2
Application number	US-201514744344-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jun 19, 2014
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

First claim

What is claimed is:

1. An apparatus comprising:
a preamplifier stage including:
a first output;
a second output;
a current source;
a PMOS differential pair coupled to a power supply side of the preamplifier stage, sources of the PMOS differential pair being coupled to the current source;
an NMOS differential pair coupled to a ground side of the preamplifier stage, a drain of a first NMOS transistor in the NMOS differential pair being coupled to a drain of a first PMOS transistor in the PMOS differential pair and to the first output, a drain of a second NMOS transistor in the NMOS differential pair being coupled to a drain of a second PMOS transistor in the PMOS differential pair and to the second output; and
a first diode-connected device coupled between the first output and a ground node; and
a second diode-connected device coupled between the second output and the ground node;
wherein the preamplifier stage further comprises a cross-coupled circuit coupled to the first diode-connected device to adjust a gain of the preamplifier stage.

2. The apparatus of claim 1 wherein the preamplifier stage further comprises one or more short-channel devices to regulate the current through the preamplifier stage.

3. The An apparatus comprising:
a preamplifier stage including:
a first output;
a second output;
a current source;
a PMOS differential pair coupled to a power supply side of the preamplifier stage, sources of the PMOS differential pair being coupled to the current source;
an NMOS differential pair coupled to a ground side of the preamplifier stage, a drain of a first NMOS transistor in the NMOS differential pair being coupled to a drain of a first PMOS transistor in the PMOS differential pair and to the first output, a drain of a second NMOS transistor in the NMOS differential pair being coupled to a drain of a second PMOS transistor in the PMOS differential pair and to the second output;
a first diode-connected device coupled between the first output and a ground node; and
a second diode-connected device coupled between the second output and the ground node; and
a feedback loop coupled to the preamplifier stage, wherein the feedback loop controls a gate voltage of a short-channel device wherein the short-channel device is coupled to the sources of the PMOS differential pair;
wherein the preamplifier stage further comprises a resistive feedback circuit coupled to the first diode-connected device to adjust a gain of the preamplifier stage.

4. An analog-to-digital converter comprising:
a preamplifier stage including:
an output including a first output node and a second output node;
a complementary circuit including:
a current source;
a PMOS differential pair coupled to a power supply side of the preamplifier stage, sources of the PMOS differential pair being coupled to the current source; and
an NMOS differential pair coupled to a ground side of the preamplifier stage, a drain of a first NMOS transistor in the NMOS differential pair being coupled to a drain of a first PMOS transistor in the PMOS differential pair and to the first output node, a drain of a second NMOS transistor in the NMOS differential pair being coupled to a drain of a second PMOS transistor in the PMOS differential pair and to the second output node;

a first diode-connected device coupled between the first output node and a ground; and
a second diode-connected device coupled between the second output node and the ground, the analog-to-digital converter further comprising:

a telescopic amplifier stage coupled to the preamplifier stage to receive and amplify the output of the preamplifier stage producing an amplified output; and
analog-to-digital conversion logic to receive the amplified output of the telescopic stage and generate a digital signal based on the received, amplified output of the telescopic amplifier stage;
wherein the preamplifier stage further comprises a cross-coupled circuit coupled to the first and second diode-connected devices to adjust a gain of the preamplifier stage.

5. An apparatus comprising:
a preamplifier stage including:
a first output;
a second output;
a current source;
a PMOS differential pair coupled to a power supply side of the preamplifier stage, sources of the PMOS differential pair being coupled to the current source;
an NMOS differential pair coupled to a ground side of the preamplifier stage, a drain of a first NMOS transistor in the NMOS differential pair being coupled to a drain of a first PMOS transistor in the PMOS differential pair and to the first output, a drain of a second NMOS transistor in the NMOS differential pair being coupled to a drain of a second PMOS transistor in the PMOS differential pair and to the second output; and
a first diode-connected device coupled between the first output and a ground node; and
a second diode-connected device coupled between the second output and the ground node;

wherein the preamplifier stage further comprises a first resistive feedback circuit coupled to the first diode-connected device and a second resistive feedback circuit coupled to the second diode-connected device to adjust a gain of the preamplifier stage.

6. A method comprising:
receiving, by a preamplifier stage, a power supply voltage and a differential input;
generating, by the preamplifier stage, an output based upon the differential input;
reusing, by a complimentary circuit, a current through the preamplifier stage, the complementary circuit including a PMOS differential pair coupled to a power supply side of the preamplifier stage, and an NMOS differential pair coupled to a ground side of the preamplifier stage, sources of the PMOS differential pair being coupled to a current source, a drain of a first NMOS transistor in the NMOS differential pair being coupled to a drain of a first PMOS transistor in the PMOS differential pair and to a first output node, a drain of a second NMOS transistor in the NMOS differential pair being coupled to a drain of a second PMOS transistor in the PMOS differential pair and to a second output node;
biasing the first output node with a first diode-connected device coupled between the first output node and a ground node; and

biasing the second output node with a second diode-connected device coupled between the second output node and the ground node;
further comprising adjusting a gain of the preamplifier stage using a first resistive feedback circuit coupled to the first diode-connected device and a second resistive feedback circuit coupled to the second diode-connected device.

Assignees

• Texas Instruments Inc

Inventors

• Hsieh Tien-Ling

Classifications

• H03F2203/45644

  the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors · CPC title

• H03F2200/36

  the amplifier comprising means for increasing the bandwidth · CPC title

• H03F2203/45674

  the LC comprising one current mirror · CPC title

• H03F3/45565

  Controlling the active amplifying circuit of the differential amplifier · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title