Method of generating a pulse width modulation (PWM) signal for an analog amplifier, and a related pulse width modulator

Patent metadata

Field	Value
Publication number	US-10044326-B2
Application number	US-201414914768-A
Country	US
Kind code	B2
Filing date	Oct 10, 2014
Priority date	Oct 11, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A method (300) of generating a pulse width modulation (PWM) signal for an analog amplifier, the amplifier arranged to receive an amplifier input signal having a magnitude, is disclosed. The method comprises receiving (302) a modulator input signal, which is associated with the amplifier input signal; and using (304) the modulator input signal to modulate a carrier to produce the PWM signal, wherein the carrier's frequency varies in dependence on the magnitude of the amplifier input signal. A related pulse width modulator is also disclosed.

First claim

The invention claimed is:

1. A method of generating a phase-adjusted pulse width modulation (PWM) signal for an analog amplifier, the amplifier arranged to receive an amplifier input signal, the method comprising:
(i) receiving a modulator input signal, which is associated with the amplifier input signal;
(ii) using the modulator input signal to modulate a carrier to produce a PWM signal having a series of pulses; and
(iii) adjusting the pulses of the PWM signal to produce the phase-adjusted PWM signal, the phase-adjusted PWM signal including a series of phase-adjusted pulses with each phase-adjusted pulse defined by a pair of changing edges and a pulse center, the pulse center of each phase-adjusted pulse being fixed relative to a respective center of the carrier, and with one of the changing edges being synchronized to a triggering edge of the PWM signal.

2. The method according to claim 1 , wherein the pulse center of each phase-adjusted pulse is in registration with the respective center of the carrier.

3. The method according to claim 1 , wherein the fixed relative position between the pulse center of each phase-adjusted pulse and the respective center of the carrier includes a constant time delay which is independent of the magnitude of the input signal.

4. A pulse width modulator for generating a phase-adjusted pulse width modulation (PWM) signal for an analog amplifier, the amplifier arranged to receive an amplifier input signal, the pulse width modulator comprising:
(i) a modulator input for receiving a modulator input signal, which is associated with the amplifier input signal,
(ii) a modulator for modulating a carrier with the modulator input signal to produce a PWM signal having a series of pulses, and
(iii) a pulse circuit for adjusting the pulses of the PWM signal to produce the phase-adjusted PWM signal, the phase-adjusted PWM signal including a series of phase-adjusted pulses with each phase-adjusted pulse defined by a pair of changing edges and a pulse center, the pulse center of each phase-adjusted pulse being fixed relative to a respective center of the carrier, and with one of the changing edges being synchronized to a triggering edge of the PWM signal.

5. The pulse width modulator according to claim 4 , wherein the pulse center of each phase-adjusted pulse is in registration with the respective center of the carrier.

6. The pulse width modulator according to claim 4 , wherein the fixed relative position between the pulse center of each phase-adjusted pulse and the respective center of the carrier includes a constant time delay which is independent of the magnitude of the input signal.

7. The pulse width modulator according to claim 4 , wherein the modulator includes at least a first comparator configured to modulate the carrier with the modulator input signal to produce the PWM signal.

8. The pulse width modulator according to claim 7 , wherein the modulator further includes at least one sample-and-hold device arranged to receive signals from the first comparator, and a second comparator arranged to receive signals from the sample-and-hold device.

9. The pulse width modulator according to claim 8 , wherein the second comparator is arranged to produce the phase-adjusted PWM signal.

10. The pulse width modulator according to claim 8 , wherein the modulator further includes at least a pulse combining circuit arranged to receive signals from the first and second comparators to produce the phase-adjusted PWM signal.

11. The pulse width modulator according to claim 7 , wherein the modulator further includes at least one half pulse generator arranged to receive signals from the first comparator, and at least one pulse doubler arranged to receive signals from the half pulse generator to produce the phase-adjusted PWM signal.

12. An analog amplifier comprising:
a pulse width modulator for generating a phase-adjusted pulse width modulation (PWM) signal for the amplifier, the pulse width modulator including
(i) a modulator input for receiving a modulator input signal, which is associated with an amplifier input signal of the amplifier,
(ii) a modulator for modulating a carrier with the modulator input signal to produce a PWM signal having a series of pulses, and
(iii) a pulse circuit for adjusting the pulses of the PWM signal to produce the phase-adjusted PWM signal, the phase-adjusted PWM signal including a series of phase-adjusted pulses with each phase-adjusted pulse defined by a pair of changing edges and a pulse center, the pulse center of each phase-adjusted pulse being fixed relative to a respective center of the carrier, and with one of the changing edges being synchronized to a triggering edge of the PWM signal.

13. The analog amplifier according to claim 12 , wherein the amplifier is a Class D analog amplifier.

14. The analog amplifier according to claim 12 , further comprising an integrator and filter circuit arranged to filter the amplifier input signal to produce the modulator input signal.

15. The analog amplifier according to claim 12 , further comprising a carrier generator arranged to generate the carrier.

Assignees

• Univ Nanyang Tech

Inventors

• Chang Joseph Sylvester
• Ge Tong
• Guo Linfei

Classifications

• H03F3/2175

  using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03F3/187 Primary

  in integrated circuits · CPC title

• H03F2203/45526

  the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC · CPC title

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title