System and method for linearizing a transmitter by rejecting harmonics at mixer output

Patent metadata

Field	Value
Publication number	US-10044321-B2
Application number	US-201615277534-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Aug 2, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BB I , a second input for receiving BB I , a third input for receiving BB Q , a fourth input for receiving BB Q , a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of passive mixers, wherein each of the plurality of passive mixers includes a first input for receiving a baseband in-phase signal BB I , a second input for receiving an inverse of the baseband in-phase signal BB I , a third input for receiving a baseband quadrature signal BB Q , a fourth input for receiving an inverse of the baseband quadrature signal BB Q , a fifth input for receiving a first clock signal with a unique phase shift within one of the plurality of passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the plurality of passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the plurality of passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the plurality of passive mixers, and at least one output; and
a voltage-domain vector summation array connected to the output of each of the plurality of passive mixers, wherein the voltage-domain vector summation array is comprised of capacitors
and wherein the capacitors are comprised of:
a first capacitor, including a first terminal connected to the at least one output of the first passive mixer, and a second terminal;
a second capacitor, including a first terminal connected to the at least one output of the second passive mixer, and a second terminal connected to the second terminal of the first capacitor; and
a third capacitor, including a first terminal connected to the at least one output of the third passive mixer, and a second terminal connected to the second terminal of the first capacitor,

wherein the first capacitor has a weight of substantially C,
the second capacitor has a weight of substantially 0.7 C, and
the third capacitor has a weight of substantially 0.7 C.

2. The apparatus of claim 1 , wherein the capacitors are weighted.

3. The apparatus of claim 1 , wherein the plurality of passive mixers is comprised of:
a first passive mixer configured to receive a clock signal at the second input with a reference phase shift;
a second passive mixer configured to receive a clock signal at the second input with a leading phase shift relative to the reference phase shift; and
a third passive mixer configured to receive a clock signal at the second input with a lagging phase shift relative to the reference phase shift.

4. The apparatus of claim 3 , wherein the reference phase shift is a 0 degree phase shift, the leading phase shift is a +45 degree phase shift, and the lagging phase shift is a −45 degree phase shift.

5. The apparatus of claim 3 , wherein each of the first passive mixer, the second passive mixer, and the third passive mixer is comprised of:
a first n-channel metal oxide semiconductor field effect transistor (NMOSFET), including a source connected to the first input of a corresponding passive mixer, a gate connected to the fifth input of the corresponding passive mixer, and a drain connected to the at least one output of the corresponding passive mixer;
a second NMOSFET, including a source connected to the second input of the corresponding passive mixer, a gate connected to the sixth input of the corresponding passive mixer, and a drain connected to the at least one output of the corresponding passive mixer;
a third NMOSFET, including a source connected to the third input of the corresponding passive mixer, a gate connected to the seventh input of the corresponding passive mixer, and a drain connected to the at least one output of the corresponding passive mixer; and
a fourth NMOSFET, including a source connected to the fourth input of the corresponding passive mixer, a gate connected to the eighth input of the corresponding passive mixer, and a drain connected to the at least one output of the corresponding passive mixer.

6. The apparatus of claim 3 , wherein each of the first passive mixer, the second passive mixer, and the third passive mixer is comprised of:
a first n-channel metal oxide semiconductor field effect transistor (NMOSFET), including a source connected to the fourth input of a corresponding passive mixer, a gate connected to the seventh input of the corresponding passive mixer, and a drain connected to a first output of the at least one output of the corresponding passive mixer;
a second NMOSFET, including a source connected to the fourth input of the corresponding passive mixer, a gate connected to the eighth input of the corresponding passive mixer, and a drain connected to a second output of the at least one output of the corresponding passive mixer;
a third NMOSFET, including a source connected to the third input of the corresponding passive mixer, a gate connected to the eighth input of the corresponding passive mixer, and a drain connected to the first output of the at least one output of the corresponding passive mixer;
a fourth NMOSFET, including a source connected to the third input of the corresponding passive mixer, a gate connected to the seventh input of the corresponding passive mixer, and a drain connected to the second of the at least one output of the corresponding passive mixer;
a fifth NMOSFET, including a source connected to the first input of the corresponding passive mixer, a gate connected to the fifth input of the corresponding passive mixer, and a drain connected to the first output of the at least one output of the corresponding passive mixer;
a sixth NMOSFET, including a source connected to the first input of the corresponding passive mixer, a gate connected to the sixth input of the corresponding passive mixer, and a drain connected to the second output of the at least one output of the corresponding passive mixer;
a seventh NMOSFET, including a source connected to the second input of the corresponding passive mixer, a gate connected to the sixth input of the corresponding passive mixer, and a drain connected to the first output of the at least one output of the corresponding passive mixer; and
an eighth NMOSFET, including a source connected to the second input of the corresponding passive mixer, a gate connected to the fifth input of the corresponding passive mixer, and a drain connected to the second output of the at least one output of the corresponding passive mixer.

7. A method, comprising:
mixing, by a plurality of passive mixers, a baseband in-phase signal BB I , an inverse of the baseband in-phase signal BB I , a baseband quadrature signal BB Q , and an inverse of the baseband quadrature signal BB Q , wherein each of the plurality of passive mixers includes a first input for receiving BB I , a second input for receiving BB I , a third input for receiving BB Q , a fourth input for receiving BB Q , a fifth input for receiving a first clock signal with a unique phase shift within one of the plurality of passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the plurality of passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the plurality of passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the plurality of passive mixers, and at least one output; and
summing the mixed BB I , BB I , BB Q , and BB Q by a voltage-domain vector summation array connected to the output of each of the plurality of passive mixers, wherein the voltage-domain vector summation array is comprised of capacitors; and
wherein the capacitors are comprised of:
a first capacitor, including a first terminal connected to the at least one output of the first passive mixer, and a second terminal;
a second capacitor, including a first terminal connected to the at least o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bhagavatula Venumadhav
• LU Siuchuang Ivan
• Son Sang Won

Classifications

• H03D2200/0086

  Reduction or prevention of harmonic frequencies · CPC title

• H03D7/1466 Primary

  Passive mixer arrangements · CPC title

• H03D7/1483

  comprising components for selecting a particular frequency component of the output · CPC title

• H03D7/165

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

• H03D7/1441

  using field-effect transistors (H03D7/145 takes precedence) · CPC title