Transistor amplifier circuit and integrated circuit

Patent metadata

Field	Value
Publication number	US-10043894-B2
Application number	US-201414542990-A
Country	US
Kind code	B2
Filing date	Nov 17, 2014
Priority date	Nov 28, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

First claim

The invention claimed is:

1. A transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the laterally extended second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the laterally extended second region, wherein the laterally extended second region separates the portion from the second p-n junction, and wherein the transistor further comprises:
a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region, wherein the doped region has a higher doping concentration than the laterally extended second region; and
a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region.

2. The transistor of claim 1 , wherein the maximum concentration of the doping in the doped region optionally is in the range of 10 17 -10 19 cm −3 .

3. The transistor of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

4. The transistor of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

5. The transistor of claim 1 , wherein the first region is an emitter region, the intermediate region is a base region and the laterally extended second region is a collector region, wherein the collector region is formed in the substrate, the base region is formed on the collector region and the emitter region is formed on the base region.

6. The transistor of claim 5 , wherein the portion is laterally separated from the second p-n junction by a trench insulation region, said collector region extending from the second p-n junction to the portion underneath the trench insulation region.

7. The transistor of claim 5 , wherein the collector region has a thickness in the range of 0.1-1.0 μm and a concentration of an impurity of the first conductivity type in the range of 10 16 -10 19 cm −3 .

8. The transistor of claim 5 , wherein the collector region laterally extends over a width in the range of 0.5-5.0 μm.

9. The transistor of claim 5 , wherein the transistor is a heterojunction bipolar transistor comprising a SiGe base region.

10. The transistor of claim 1 , wherein the first region is an emitter region, the intermediate region is a base region and the laterally extended second region is a collector region, wherein the emitter region, the base region and the collector region each are formed in the substrate and laterally separated from each other, and wherein the emitter region and the base region are separated from the doped region by a patterned electrically insulating layer.

11. The transistor of claim 1 , wherein the first region is a source region and the second region is a drain region including a drift region, and wherein the intermediate region is a well comprising the first region, the transistor further comprising a channel region in between the source region and the drain region.

12. An amplifier circuit comprising the transistor of claim 1 .

13. The amplifier circuit of claim 12 , wherein the amplifier circuit is a RF amplifier.

14. An integrated circuit comprising the transistor of claim 1 .

15. The integrated circuit of claim 14 , wherein the transistor is included in an amplifier circuit.

Assignees

• Nxp Bv

Inventors

• Dinh Viet Thanh
• Vanhoucke Tony
• Gridelet Evelyne
• Heringa Anco
• Slotboom Jan Willem
• Klaassen Dirk

Classifications

• H01L29/7371 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic

• H01L29/7378

  Electricity · mapped topic